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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

IEEE journal of solid-state circuits, 2024-08, p.1-9

2024

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A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

IEEE transactions on very large scale integration (VLSI) systems, 2018-11, Vol.26 (11), p.2335-2344

2018

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A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low- V MIN Applications

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.179-187

2021

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Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros

IEEE transactions on computer-aided design of integrated circuits and systems, 2024-04, Vol.43 (4), p.1191-1205

2024

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A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

IEEE journal of solid-state circuits, 2021-01, Vol.56 (1), p.179-187

2021

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An inter-die variability compensation scheme for 0.42-V 486-kb FD-SOI SRAM using substrate control

2008 IEEE International SOI Conference, 2008, p.93-94

2008

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A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

IEEE journal of solid-state circuits, 2011-11, Vol.46 (11), p.2535-2544

2011

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.572-574

2024

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A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023, p.1-2

2023

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24.4 A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.1-3

2021

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A 4nm 6163-TOPS/W/b \mathbf/b} SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update

2023 IEEE International Solid- State Circuits Conference (ISSCC), 2023, p.132-134

2023

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20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices

2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024, Vol.67, p.360-362

2024

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A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022, p.24-25

2022

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15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.238-240

2020

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A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022, Vol.65, p.1-3

2022

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16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

2021 IEEE International Solid- State Circuits Conference (ISSCC), 2021, Vol.64, p.252-254

2021

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An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

2007 IEEE Symposium on VLSI Circuits, 2007, p.256-257

2007

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Which is the best dual-port SRAM in 45-nm process technology? - 8T, 10T single end, and 10T differential

2008 IEEE International Conference on Integrated Circuit Design and Technology and Tutorial, 2008, p.55-58

2008

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24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.390-392

2019

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Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

IEEE transactions on very large scale integration (VLSI) systems, 2008-06, Vol.16 (6), p.620-627

2008

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12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.206-207

2017

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A stable chip-ID generating physical uncloneable function using random address errors in SRAM

2012 IEEE International SOC Conference, 2012, p.143-147

2012

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A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

2012 IEEE International Solid-State Circuits Conference, 2012, p.236-238

2012

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A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

2012 IEEE 21st Asian Test Symposium, 2012, p.246-251

2012

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3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM With Leakage Saving Circuits in 3-nm FinFET for HPC Applications

A 28-nm 1R1W Two-Port 8T SRAM Macro With Screening Circuitry Against Read Disturbance and Wordline Coupling Noise Failures

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low- V MIN Applications

Efficient Processing of MLPerf Mobile Workloads Using Digital Compute-In-Memory Macros

A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

An inter-die variability compensation scheme for 0.42-V 486-kb FD-SOI SRAM using substrate control

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications

34.4 A 3nm, 32.5TOPS/W, 55.0TOPS/mm2 and 3.78Mb/mm2 Fully-Digital Compute-in-Memory Macro Supporting INT12 × INT12 with a Parallel-MAC Architecture and Foundry 6T-SRAM Bit Cell

A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications

24.4 A 5nm 5.7GHz@1.0V and 1.3GHz@0.5V 4kb Standard-Cell- Based Two-Port Register File with a 16T Bitcell with No Half-Selection Issue

A 4nm 6163-TOPS/W/b \mathbf/b} SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update

20.1 NVE: A 3nm 23.2TOPS/W 12b-Digital-CIM-Based Neural Engine for High-Resolution Visual-Quality Enhancement on Smart Devices

A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications

15.1 A 5nm 135Mb SRAM in EUV and High-Mobility-Channel FinFET Technology with Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications

A 5-nm 254-TOPS/W 221-TOPS/mm2 Fully-Digital Computing-in-Memory Macro Supporting Wide-Range Dynamic-Voltage-Frequency Scaling and Simultaneous MAC and Write Operations

16.4 An 89TOPS/W and 16.3TOPS/mm2 All-Digital SRAM-Based Full-Precision Compute-In Memory Macro in 22nm for Machine-Learning Edge Applications

An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment

Which is the best dual-port SRAM in 45-nm process technology? - 8T, 10T single end, and 10T differential

24.2 A 7nm 2.1GHz Dual-Port SRAM with WL-RC Optimization and Dummy-Read-Recovery Circuitry to Mitigate Read- Disturb-Write Issue

Novel Video Memory Reduces 45% of Bitline Power Using Majority Logic and Data-Bit Reordering

12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applications

A stable chip-ID generating physical uncloneable function using random address errors in SRAM

A 28nm 360ps-access-time two-port SRAM with a time-sharing scheme to circumvent read disturbs

A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

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