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The physical design of on-chip interconnections

IEEE transactions on computer-aided design of integrated circuits and systems, 2003-03, Vol.22 (3), p.254-276

2003

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A 4.6GHz resonant global clock distribution network

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.342-343 Vol.1

First edition, 2004

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A 640-ps, 0.25-/spl mu/m CMOS, 16/spl times/64-b three-port register file

IEEE journal of solid-state circuits, 1997-08, Vol.32 (8), p.1288-1292

1997

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A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

IEEE journal of solid-state circuits, 1997-08, Vol.32 (8), p.1288-1292

1997

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A room temperature 0.1 μm CMOS on SOI

IEEE transactions on electron devices, 1994-12, Vol.41 (12), p.2405-2412

1994

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Timing uncertainty measurements on the Power5 microprocessor

2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519), 2004, p.354-355 Vol.1

First edition, 2004

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A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1577-1585

1991

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A large V/sub DS/ data retention test pattern for DRAM's

IEEE journal of solid-state circuits, 1992-08, Vol.27 (8), p.1214-1217

1992

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Measurement of VLSI power supply current by electron-beam probing

IEEE journal of solid-state circuits, 1992-06, Vol.27 (6), p.948-950

1992

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Advances In Membrane Probe Technology

Proceedings International Test Conference 1992, 1992, p.927

1992

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A 4-Mb low-temperature DRAM

IEEE journal of solid-state circuits, 1991-11, Vol.26 (11), p.1519-1529

1991

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A room temperature 0.1 /spl mu/m CMOS on SOI

IEEE transactions on electron devices, 1994-12, Vol.41 (12), p.2405-2412

1994

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On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM

IEEE journal of solid-state circuits, 1992-07, Vol.27 (7), p.1073-1079

1992

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Fast CMOS ECL receivers with 100-mV worst-case sensitivity

IEEE journal of solid-state circuits, 1988-02, Vol.23 (1), p.59-67

1988

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A 12-ns low-temperature DRAM

IEEE transactions on electron devices, 1989-08, Vol.36 (8), p.1414-1422

1989

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A 20-ns 128-kbit4 high speed DRAM with 330-Mbit/s data rate

IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1140-1149

1988

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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

1989

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A subnanosecond 5-kbit bipolar ECL RAM

IEEE journal of solid-state circuits, 1988-10, Vol.23 (5), p.1265-1267

1988

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A 15-ns CMOS 64K RAM

IEEE journal of solid-state circuits, 1986-10, Vol.21 (5), p.704-712

1986

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Micro/370: a 32-bit single-chip microprocessor

IEEE journal of solid-state circuits, 1986-10, Vol.21 (5), p.733-740

1986

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On-Chip Test Circuitry for a 2 ns Cycle 512Kb CMOS ECL SRAM

ESSCIRC '91: Proceedings - Seventeenth European Solid-State Circuits Conference, 1991, Vol.1, p.209-212

1991

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A 1.2 ns/1 ns 1 K16 ECL dual-port cache RAM

1993 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 1993, p.244-245

1993

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A 4 Mb Low-temperature DRAM

1991 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1991, p.30-31

1991

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A low temperature 12 ns DRAM

International Symposium on VLSI Technology, Systems and Applications, 1989, p.32-35

1989

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Low temperature SER and noise in a high speed DRAM

Proceedings of the Workshop on Low Temperature Semiconductor Electronics, 1989, p.5-9

1989

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The physical design of on-chip interconnections

A 4.6GHz resonant global clock distribution network

A 640-ps, 0.25-/spl mu/m CMOS, 16/spl times/64-b three-port register file

A 640-ps, 0.25-μm CMOS, 16×64-b three-port register file

A room temperature 0.1 μm CMOS on SOI

Timing uncertainty measurements on the Power5 microprocessor

A 2-ns cycle, 3.8-ns access 512-kb CMOS ECL SRAM with a fully pipelined architecture

A large V/sub DS/ data retention test pattern for DRAM's

Measurement of VLSI power supply current by electron-beam probing

Advances In Membrane Probe Technology

A 4-Mb low-temperature DRAM

A room temperature 0.1 /spl mu/m CMOS on SOI

On-chip test circuitry for a 2-ns cycle, 512-kb CMOS ECL SRAM

Fast CMOS ECL receivers with 100-mV worst-case sensitivity

A 12-ns low-temperature DRAM

A 20-ns 128-kbit4 high speed DRAM with 330-Mbit/s data rate

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

A subnanosecond 5-kbit bipolar ECL RAM

A 15-ns CMOS 64K RAM

Micro/370: a 32-bit single-chip microprocessor

On-Chip Test Circuitry for a 2 ns Cycle 512Kb CMOS ECL SRAM

A 1.2 ns/1 ns 1 K16 ECL dual-port cache RAM

A 4 Mb Low-temperature DRAM

A low temperature 12 ns DRAM

Low temperature SER and noise in a high speed DRAM

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