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An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

IEEE transactions on very large scale integration (VLSI) systems, 2021-02, Vol.29 (2), p.372-385

2021

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A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.38-48

2020

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A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

IEEE transactions on circuits and systems. II, Express briefs, 2024-07, Vol.71 (7), p.3318-3322

2024

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Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

Electronics letters, 2023-12, Vol.59 (23), p.n/a

2023

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A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2014-11, Vol.49 (11), p.2474-2489

2014

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Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer

Sensors and actuators. A. Physical., 2014-08, Vol.215, p.96-104

2014

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30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.476-478

2019

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A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

IEEE journal of solid-state circuits, 2013-12, Vol.48 (12), p.3049-3058

2013

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A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform

IEEE transactions on circuits and systems. II, Express briefs, 2024-06, p.1-1

2024

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Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification

IEEE transactions on computers, 2021-06, Vol.70 (6), p.922-935

2021

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A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2018-12, Vol.53 (12), p.3508-3516

2018

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A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers

IEEE transactions on circuits and systems. I, Regular papers, 2024-08, p.1-14

2024

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A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC

IEEE transactions on circuits and systems. II, Express briefs, 2024-08, p.1-1

2024

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Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2023-09, Vol.70 (9), p.3639-3643

2023

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A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2018-11, Vol.53 (11), p.3268-3279

2018

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Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

IEEE journal of solid-state circuits, 2016-03, Vol.51 (3), p.636-648

2016

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An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

IEEE journal of solid-state circuits, 2018-03, Vol.53 (3), p.861-872

2018

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A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

IEEE transactions on power electronics, 2017-01, Vol.32 (1), p.378-393

2017

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A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

IEEE journal of solid-state circuits, 2017-12, Vol.52 (12), p.3458-3473

2017

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Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

IEEE transactions on power electronics, 2017-01, Vol.32 (1), p.363-377

2017

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Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

ESSCIRC 2021 - IEEE 47th European Solid State Circuits Conference (ESSCIRC), 2021, p.67-70

2021

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A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

2018 IEEE International Solid - State Circuits Conference - (ISSCC), 2018, p.104-106

2018

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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1074-1086

2023

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An SRAM-Based Multibit In-Memory Matrix-Vector Multiplier With a Precision That Scales Linearly in Area, Time, and Power

A 161-mW 56-Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14-nm FinFET

A DAC/ADC-Based Wireline Transceiver Datapath Functional Verification on RFSoC Platform

Design of synchronous frequency dividers in 5‐nm FinFET CMOS technology

A 4×4 MIMO Discrete Multitone Wireline Transceiver With Far-End Crosstalk Cancellation For ADC-Based High-Speed Serial Links

A 32 Gb/s Backplane Transceiver With On-Chip AC-Coupling and Low Latency CDR in 32 nm SOI CMOS Technology

Wide bandwidth room-temperature THz imaging array based on antenna-coupled MOSFET bolometer

30.2 A 161mW 56Gb/s ADC-Based Discrete Multitone Wireline Receiver Data-Path in 14nm FinFET

A 3.1 mW 8b 1.2 GS/s Single-Channel Asynchronous SAR ADC With Alternate Comparators for Enhanced Speed in 32 nm Digital SOI CMOS

A 2-Lane Discrete Multitone Wireline Receiver Datapath With Far-End Crosstalk Cancellation on RFSoC Platform

Efficient Pipelined Execution of CNNs Based on In-Memory Computing and Graph Homomorphism Verification

A 24-72-GS/s 8-b Time-Interleaved SAR ADC With 2.0-3.3-pJ/Conversion and >30 dB SNDR at Nyquist in 14-nm CMOS FinFET

A Loop-Break Decision Feedback Equalizer for DAC/ADC-DSP-Based Wireline Transceivers

A Discrete Multitone Wireline Transceiver Datapath With On-Chip Sign-Sign LMS Adaptation And Loading Profile Optimization On RFSoC

Design of Time-Encoded Spiking Neural Networks in 7-nm CMOS Technology

A 12-bit 300-MS/s SAR ADC With Inverter-Based Preamplifier and Common-Mode-Regulation DAC in 14-nm CMOS FinFET

Implementation of Low-Power 6-8 b 30-90 GS/s Time-Interleaved ADCs With Optimized Input Bandwidth in 32 nm CMOS

A 64-core mixed-signal in-memory compute chip based on phase-change memory for deep neural network inference

An Eight-Lane 7-Gb/s/pin Source Synchronous Single-Ended RX With Equalization and Far-End Crosstalk Cancellation for Backplane Channels

A 10 W On-Chip Switched Capacitor Voltage Regulator With Feedforward Regulation Capability for Granular Microprocessor Power Delivery

A 64-Gb/s 1.4-pJ/b NRZ Optical Receiver Data-Path in 14-nm CMOS FinFET

Modeling and Pareto Optimization of On-Chip Switched Capacitor Converters

Cryogenic Characterization and Modeling of 14 nm Bulk FinFET Technology

A 112Gb/S 2.6pJ/b 8-Tap FFE PAM-4 SST TX in 14nm CMOS

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

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