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A single-chip false target radar image generator for countering wideband imaging radars

IEEE journal of solid-state circuits, 2002-06, Vol.37 (6), p.751-759

2002

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Modeling single-event effects in a complex digital device

IEEE transactions on nuclear science, 2003-12, Vol.50 (6), p.2069-2080

2003

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Efficient time-frequency and bi-frequency signal processing on a reconfigurable computer

2008 42nd Asilomar Conference on Signals, Systems and Computers, 2008, p.176-180

2008

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Digital false-target image synthesiser for countering ISAR

IEE proceedings. Radar, sonar, and navigation, 2002-10, Vol.149 (5), p.248

2002

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A gallium-arsenide digital phase shifter for clock and control signal distribution in high-speed digital systems

IEEE journal of solid-state circuits, 1992-05, Vol.27 (5), p.802-809

Fouts, D.J.

1992

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Effects of low-temperature buffer-layer thickness and growth temperature on the SEE sensitivity of GaAs HIGFET circuits

IEEE transactions on nuclear science, 1997-12, Vol.44 (6), p.2298-2305

1997

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A digital ASIC for synthesizing false target radar images

Conference Record of the Thirty-Sixth Asilomar Conference on Signals, Systems and Computers, 2002, 2002, Vol.2, p.1411-1415 vol.2

2002

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A phasing adjustment and fanout buffer for distributing clock and control signals in high-speed digital systems

[1991] Proceedings of the 34th Midwest Symposium on Circuits and Systems, 1991, p.974-977 vol.2

Fouts, D.J.

1991

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SEU design considerations for MESFETs on LT GaAs

IEEE transactions on nuclear science, 1997-12, Vol.44 (6), p.2282-2289

1997

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Single event upsets in gallium arsenide dynamic logic

IEEE Transactions on Nuclear Science (Institute of Electrical and Electronics Engineers); (United States), 1994-12, Vol.41 (6), p.2244-2251

1994

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Architecture and design of a 500-MHz gallium-arsenide processing element for a parallel supercomputer

IEEE journal of solid-state circuits, 1991-09, Vol.26 (9), p.1199-1211

1991

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Single event upsets in gallium arsenide pseudo-complementary MESFET logic

IEEE transactions on nuclear science, 1995-12, Vol.42 (6), p.1829-1836

1995

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Low-power High-speed Complementary Gaas Dynamic Logic Circuit Design

Proceedings of Technical Papers. International Symposium on VLSI Technology, Systems, and Applications, 1997, p.283-287

1997

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A CMOS VLSI IC for real-time opto-electronic two-dimensional histogram generation

Proceedings of 26th Southeastern Symposium on System Theory, 1994, p.390-394

1994

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A microprocessor interface for ferroelectric capacitor memory

[1992] Conference Record of the Twenty-Sixth Asilomar Conference on Signals, Systems & Computers, 1992, p.930-934 vol.2

1992

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A CMOS current-mode full-adder cell for multi-valued logic VLSI

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1997, Vol.1, p.463-467 vol.1

1997

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A dynamic four-bit carry lookahead adder circuit for complementary gallium arsenide (CGaAs) fabrication processes

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1997, Vol.2, p.1103-1106 vol.2

1997

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Soft error immune GaAs circuit technologies

Proceedings of 40th Midwest Symposium on Circuits and Systems. Dedicated to the Memory of Professor Mac Van Valkenburg, 1997, Vol.2, p.1116-1119 vol.2

1997

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