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Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

IEEE electron device letters, 2005-08, Vol.26 (8), p.579-582

2005

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Physical insights regarding design and performance of independent-gate FinFETs

IEEE transactions on electron devices, 2005-10, Vol.52 (10), p.2198-2206

2005

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Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

IEEE electron device letters, 2004-11, Vol.25 (11), p.731-733

2004

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Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs

IEEE transactions on electron devices, 2002-02, Vol.49 (2), p.287-294

2002

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On the feasibility of nanoscale triple-gate CMOS transistors

IEEE transactions on electron devices, 2005-06, Vol.52 (6), p.1159-1164

2005

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Physical Insights on BJT-Based 1T DRAM Cells

IEEE electron device letters, 2009-05, Vol.30 (5), p.565-567

2009

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Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

IEEE transactions on electron devices, 2001-02, Vol.48 (2), p.294-299

2001

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Scaling fully depleted SOI CMOS

IEEE transactions on electron devices, 2003-10, Vol.50 (10), p.2095-2103

2003

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Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate-Source/Drain Underlap

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.2143-2150

2006

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Suppression of corner effects in triple-gate MOSFETs

IEEE electron device letters, 2003-12, Vol.24 (12), p.745-747

2003

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Design Optimization and Performance Projections of Double-Gate FinFETs With Gate-Source/Drain Underlap for SRAM Application

IEEE transactions on electron devices, 2007-08, Vol.54 (8), p.1934-1942

2007

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The ITFET: A Novel FinFET-Based Hybrid Device

IEEE transactions on electron devices, 2006-09, Vol.53 (9), p.2335-2343

2006

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Speed superiority of scaled double-gate CMOS

IEEE transactions on electron devices, 2002-05, Vol.49 (5), p.808-811

2002

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Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels

IEEE transactions on electron devices, 2003-04, Vol.50 (4), p.1042-1049

2003

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Bulk inversion in FinFETs and implied insights on effective gate width

IEEE transactions on electron devices, 2005-09, Vol.52 (9), p.1993-1997

2005

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New Insights on "Capacitorless" Floating-Body DRAM Cells

IEEE electron device letters, 2007-06, Vol.28 (6), p.513-516

2007

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Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

IEEE transactions on electron devices, 2009-10, Vol.56 (10), p.2348-2353

2009

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Physical insights on electron mobility in contemporary FinFETs

IEEE electron device letters, 2006-06, Vol.27 (6), p.482-485

2006

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Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits

IEEE transactions on electron devices, 2001-09, Vol.48 (9), p.2074-2080

2001

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DICE: A Beneficial Short-Channel Effect in Nanoscale Double-Gate MOSFETs

IEEE transactions on electron devices, 2008-03, Vol.55 (3), p.796-802

2008

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A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

IEEE transactions on electron devices, 2008-06, Vol.55 (6), p.1511-1518

2008

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A Simplified Superior Floating-Body/Gate DRAM Cell

IEEE electron device letters, 2009-03, Vol.30 (3), p.282-284

2009

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Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology

IEEE transactions on electron devices, 1995-09, Vol.42 (9), p.1605-1613

1995

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On the Threshold Voltage of Strained- $hbox Si hbox -- hbox Si_1-xhbox Ge_x$ MOSFETs

IEEE transactions on electron devices, 2005-02, Vol.52 (2), p.263-268

2005

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On the performance advantage of PD/SOI CMOS with floating bodies

IEEE transactions on electron devices, 2002-01, Vol.49 (1), p.96-104

2002

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Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs

Physical insights regarding design and performance of independent-gate FinFETs

Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs

Analytical modeling of quantization and volume inversion in thin Si-film DG MOSFETs

On the feasibility of nanoscale triple-gate CMOS transistors

Physical Insights on BJT-Based 1T DRAM Cells

Double-gate CMOS: symmetrical- versus asymmetrical-gate devices

Scaling fully depleted SOI CMOS

Modeling and Significance of Fringe Capacitance in Nonclassical CMOS Devices With Gate-Source/Drain Underlap

Suppression of corner effects in triple-gate MOSFETs

Design Optimization and Performance Projections of Double-Gate FinFETs With Gate-Source/Drain Underlap for SRAM Application

The ITFET: A Novel FinFET-Based Hybrid Device

Speed superiority of scaled double-gate CMOS

Performance projections of scaled CMOS devices and circuits with strained Si-on-SiGe channels

Bulk inversion in FinFETs and implied insights on effective gate width

New Insights on "Capacitorless" Floating-Body DRAM Cells

Threshold Voltage Adjustment in Nanoscale DG FinFETs Via Limited Source/Drain Dopants in the Channel

Physical insights on electron mobility in contemporary FinFETs

Physical compact modeling and analysis of velocity overshoot in extremely scaled CMOS devices and circuits

DICE: A Beneficial Short-Channel Effect in Nanoscale Double-Gate MOSFETs

A Novel Two-Transistor Floating-Body/Gate Cell for Low-Power Nanoscale Embedded DRAM

A Simplified Superior Floating-Body/Gate DRAM Cell

Physical subthreshold MOSFET modeling applied to viable design of deep-submicrometer fully depleted SOI low-voltage CMOS technology

On the Threshold Voltage of Strained- $hbox Si hbox -- hbox Si_1-xhbox Ge_x$ MOSFETs

On the performance advantage of PD/SOI CMOS with floating bodies

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