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Addressing system-level trimming issues in on-chip nanophotonic networks

2011 IEEE 17th International Symposium on High Performance Computer Architecture, 2011, p.122-131

2011

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HLS: combining statistical and symbolic simulation to guide microprocessor designs

International Symposium on Computer Architecture: Proceedings of the 27th annual international symposium on Computer architecture : Vancouver, British Columbia, Canada, 2000, p.71-82

2000

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DCOF-An Arbitration Free Directly Connected Optical Fabric

IEEE journal on emerging and selected topics in circuits and systems, 2012-06, Vol.2 (2), p.169-182

2012

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Exploiting ILP in page-based intelligent memory

MICRO-32. Proceedings of the 32nd Annual ACM/IEEE International Symposium on Microarchitecture, 1999, p.208-218

1999

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Techniques for increasing effective data bandwidth

2008 IEEE International Conference on Computer Design, 2008, p.514-519

2008

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Code Partitioning in Decoupled Compilers

Euro-Par 2000 Parallel Processing, 2000, p.1008-1017

2000

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The Decoupled-Style Prefetch Architecture

Euro-Par 2000 Parallel Processing, 2000, p.989-993

2000

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A modified approach to data cache management

Proceedings of the 28th Annual International Symposium on Microarchitecture, 1995, p.93-103

1995

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Design and evaluation of an optical CPU-DRAM interconnect

2008 IEEE International Conference on Computer Design, 2008, p.492-497

2008

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Implementation of the PIPE processor

Computer (Long Beach, Calif.), 1991-01, Vol.24 (1), p.65-70

1991

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Monte Carlo calculations for specimens with microstructures

Scanning, 1995-07, Vol.17 (4), p.220-226

1995

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Eager writeback-a technique for improving bandwidth utilization

Proceedings 33rd Annual IEEE/ACM International Symposium on Microarchitecture. MICRO-33 2000, 2000, p.11-21

2000

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DCAF - A Directly Connected Arbitration-Free Photonic Crossbar for Energy-Efficient High Performance Computing

2012 IEEE 26th International Parallel and Distributed Processing Symposium, 2012, p.1144-1155

2012

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Inferring packet dependencies to improve trace based simulation of on-chip networks

Proceedings of the Fifth ACM/IEEE International Symposium, 2011, p.153-160

2011

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Minimizing the Data Transfer Time Using Multicore End-System Aware Flow Bifurcation

2012 12th IEEE/ACM International Symposium on Cluster, Cloud and Grid Computing (ccgrid 2012), 2012, p.595-602

2012

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A study of single-chip processor/cache organizations for large numbers of transistors

Computer architecture news, 1994-04, Vol.22 (2), p.338-347

1994

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A study of single-chip processor/cache organizations for large numbers of transistors

International Symposium on Computer Architecture: Proceedings of the 21st annual international symposium on Computer architecture : Chicago, Illinois, United States; 18-21 Apr. 1994, 1994, p.338-347

1994

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Improving performance of small on-chip instruction caches

International Symposium on Computer Architecture: Proceedings of the 16th annual international symposium on Computer architecture : Jerusalem, Israel, 1989, p.234-241

1989

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