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A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement

2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS), 2017, p.583-586

2017

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IEEE_Xplore

A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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IEEE_Xplore

A low-latency, low-overhead encoder for data transmission in the ATLAS Liquid Argon Calorimeter trigger upgrade

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2016-09, Vol.831 (C), p.288-294

2016

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A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration

IEEE journal of solid-state circuits, 2020-08, Vol.55 (8), p.2082-2093

2020

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IEEE_Xplore

A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

IEEE solid-state circuits letters, 2019-09, Vol.2 (9), p.99-102

2019

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IEEE_Xplore

A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-5

2019

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IEEE_Xplore

A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.301-304

2019

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IEEE_Xplore

A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.99-102

2019

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IEEE_Xplore

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation

IEEE transactions on very large scale integration (VLSI) systems, 2022-05, Vol.30 (5), p.625-633

2022

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IEEE_Xplore

On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

IEEE transactions on nuclear science, 2023-03, Vol.70 (3), p.1-1

2023

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IEEE_Xplore

Design and Calibration of Power-Efficient High-Speed SAR-Based ADCs

Fan, Qingjun

2020

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ProQuest

Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.265-268

2020

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IEEE_Xplore

A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-4

2020

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IEEE_Xplore

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference (ESSCIRC), 2019, p.193-196

2019

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IEEE_Xplore

A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications

2020 IEEE International Symposium on Circuits and Systems (ISCAS), 2020, p.1-4

2020

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IEEE_Xplore

RFI mitigating receiver back-end for radiometers

2017 IEEE International Geoscience and Remote Sensing Symposium (IGARSS), 2017, p.1255-1258

2017

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IEEE_Xplore

A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS

2019 IEEE International Symposium on Circuits and Systems (ISCAS), 2019, p.1-4

2019

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IEEE_Xplore

A radiation-tolerant DLL with fine resolution and duty cycle corrector for memory interface

2016 IEEE Dallas Circuits and Systems Conference (DCAS), 2016, p.1-5

2016

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IEEE_Xplore

Mechanical Behavior and Failure Mechanism of Recycled Semi-flexible Pavement Material

Journal of Wuhan University of Technology. Materials science edition, 2015-10, Vol.30 (5), p.981-988

2015

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A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications

2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, p.171-174

2018

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IEEE_Xplore

A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS

2018 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2018, p.30-33

2018

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IEEE_Xplore

An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology

2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS), 2020, p.1-4

2020

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IEEE_Xplore

Migration capacity of human umbilical cord mesenchymal stem cells towards glioma in vivo

Neural regeneration research, 2013-08, Vol.8 (22), p.2093-2102

2013

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A wideband complementary noise and distortion canceling LNA for high-frequency ultrasound imaging applications

2018 Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), 2018, p.1-4

2018

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IEEE_Xplore

A Wide Tuning Range and Low Phase Noise Quotient Frequency Synthesizer for Multiband Millimeter-Wave Applications

2019 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS), 2019, p.1-4

2019

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A 10-bit 400 MS/s asynchronous SAR ADC using dual-DAC architecture for speed enhancement

A 14-bit 2.5 GS/s digital pre-distorted DAC in 65 nm CMOS with SFDR > 70 dB up to 1.2 GHz

A low-latency, low-overhead encoder for data transmission in the ATLAS Liquid Argon Calorimeter trigger upgrade

A Time-Interleaved SAR ADC With Bypass-Based Opportunistic Adaptive Calibration

A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

A 500-MS/s 13-Bit SAR-Assisted Time-Interleaved Digital-Slope ADC

A 2.4 GS/s 10-Bit Time-Interleaved SAR ADC with a Bypass Window and Opportunistic Offset Calibration

A 1-GS/s 8-Bit 12.01-fJ/conv.-step Two-Step SAR ADC in 28-nm FDSOI Technology

A 5-GS/s 6-Bit 15.07-mW Flash ADC With Partially Active Second-Stage Comparison and 2× Time-Domain Interpolation

On-Chip Fast Signal Generation and Low-Power SAR ADC for SiPM Readout

Design and Calibration of Power-Efficient High-Speed SAR-Based ADCs

Machine-Learning Based Nonlinerity Correction for Coarse-Fine SAR-TDC Hybrid ADC

A 6-b 20-GS/s 2-Way Time-Interleaved Flash ADC with Automatic Comparator Offset Calibration in 28-nm FDSOI

A 500 MS/s 10-Bit Single-Channel SAR ADC with A Double-Rate Comparator

A Quadrature Frequency Synthesizer with 118.7-fs Jitter, 27.94% Locking Range for Multiband 5G mmW Applications

RFI mitigating receiver back-end for radiometers

A Low-Power SiPM Readout Front-End with Fast Pulse Generation and Successive-Approximation Register ADC in 0.18 μm CMOS

A radiation-tolerant DLL with fine resolution and duty cycle corrector for memory interface

Mechanical Behavior and Failure Mechanism of Recycled Semi-flexible Pavement Material

A Current Reuse Wideband LNA with Complementary Noise and Distortion Cancellation for Ultrasound Imaging Applications

A 25-GS/s 4-bit Single-core Flash ADC in 28 nm FDSOI CMOS

An Automatic Comparator Offset Calibration for High-Speed Flash ADCs in FDSOI CMOS Technology

Migration capacity of human umbilical cord mesenchymal stem cells towards glioma in vivo

A wideband complementary noise and distortion canceling LNA for high-frequency ultrasound imaging applications

A Wide Tuning Range and Low Phase Noise Quotient Frequency Synthesizer for Multiband Millimeter-Wave Applications

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