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Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

IEEE transactions on components, packaging, and manufacturing technology (2011), 2018-06, Vol.8 (6), p.991-1002

2018

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Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

IEEE transactions on components, packaging, and manufacturing technology (2011), 2017-10, Vol.7 (10), p.1729-1738

2017

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Fan-Out Wafer-Level Packaging for Heterogeneous Integration

IEEE transactions on components, packaging, and manufacturing technology (2011), 2018-09, Vol.8 (9), p.1544-1560

2018

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Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

IEEE transactions on components, packaging, and manufacturing technology (2011), 2018-10, Vol.8 (10), p.1729-1737

2018

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Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

IEEE transactions on components, packaging, and manufacturing technology (2011), 2018-09, Vol.8 (9), p.1561-1572

2018

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Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

2010 53rd IEEE International Midwest Symposium on Circuits and Systems, 2010, p.893-896

2010

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Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die

Journal of electronic packaging, 2004-03, Vol.126 (1), p.110-114

2004

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High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

IEEE microwave and wireless components letters, 2004-09, Vol.14 (9), p.449-451

2004

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Development of chip-first and die-up fan-out wafer level packaging

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), 2017, p.1-6

2017

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Optimization of packaging process in Ag sintering for ultra-reliable SiC based power electronics

2023 24th International Conference on Electronic Packaging Technology (ICEPT), 2023, p.1-4

2023

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Dispensing challenges of large format packaging and some of its possible solutions

2017 IEEE 19th Electronics Packaging Technology Conference (EPTC), 2017, p.1-6

2017

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Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

Journal of microelectronics and electronic packaging, 2017-10, Vol.14 (4), p.123-131

2017

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Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

International Symposium on Microelectronics, 2018-10, Vol.2018 (1), p.57-63

2018

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Reliability of Fan-Out Wafer-Level Heterogeneous Integration

Journal of microelectronics and electronic packaging, 2018-10, Vol.15 (4), p.148-162

2018

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Feasibility Study of Fan-Out Wafer-Level Packaging for Heterogeneous Integrations

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.903-909

2019

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Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Journal of microelectronics and electronic packaging, 2018-10, Vol.15 (4), p.141-147

2018

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Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates

IEEE transactions on components, packaging, and manufacturing technology (2011), 2015-07, Vol.5 (7), p.1027-1035

2015

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Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

2010 IEEE Workshop on Microelectronics and Electron Devices, 2010, p.1-4

2010

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Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.1574-1582

2018

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Tools for Fan‐Out Wafer‐Level Package Processing

Advances in Embedded and Fan‐Out Wafer‐Level Packaging Technologies, 2019, p.403-417

2019

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Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

2017 IEEE 67th Electronic Components and Technology Conference (ECTC), 2017, p.595-602

2017

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Feasibility Study of Fan-Out Panel-Level Packaging for Heterogeneous Integrations

2019 IEEE 69th Electronic Components and Technology Conference (ECTC), 2019, p.14-20

2019

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Challenges of Large Format Packaging and Some of Its Assembly Solutions

International Symposium on Microelectronics, 2017-10, Vol.2017 (1), p.747-753

2017

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Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Redistributed Layers

2018 IEEE 68th Electronic Components and Technology Conference (ECTC), 2018, p.594-600

2018

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Reliability of Fan-Out Wafer-Level Heterogeneous Integration

International Symposium on Microelectronics, 2018-10, Vol.2018 (1), p.224-232

2018

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Design, Materials, Process, Fabrication, and Reliability of Fan-Out Wafer-Level Packaging

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

Fan-Out Wafer-Level Packaging for Heterogeneous Integration

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging With Large Chips and Multiple Redistributed Layers

Chip-First Fan-Out Panel-Level Packaging for Heterogeneous Integration

Supply boosting technique for designing very low-voltage mixed-signal circuits in standard CMOS

Effects of Wafer Thinning Condition on the Roughness, Morphology and Fracture Strength of Silicon Die

High-performance large-inductance embedded inductors in thin array plastic packaging (TAPP) for RF system-in-package applications

Development of chip-first and die-up fan-out wafer level packaging

Optimization of packaging process in Ag sintering for ultra-reliable SiC based power electronics

Dispensing challenges of large format packaging and some of its possible solutions

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

Feasibility Study of Fan-Out Wafer-Level Packaging for Heterogeneous Integrations

Design, Materials, Process, and Fabrication of Fan-Out Panel-Level Heterogeneous Integration

Stencil Printing of Underfill for Flip Chips on Organic-Panel and Si-Wafer Substrates

Integration of a New Column-Parallel ADC Technology on CMOS Image Sensor

Reliability of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Re-Distributed Layers

Tools for Fan‐Out Wafer‐Level Package Processing

Warpage and Thermal Characterization of Fan-Out Wafer-Level Packaging

Feasibility Study of Fan-Out Panel-Level Packaging for Heterogeneous Integrations

Challenges of Large Format Packaging and Some of Its Assembly Solutions

Warpage Measurements and Characterizations of Fan-Out Wafer-Level Packaging with Large Chips and Multiple Redistributed Layers

Reliability of Fan-Out Wafer-Level Heterogeneous Integration

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