UB Paderborn / Katalog / Suche / in CDI

1 – 25 von 115

Sortiert nach

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

Solid-state electronics, 2011-11, Vol.65-66, p.94-102

2011

Link zum Volltext

Verfügbarkeit prüfen

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

2015 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 2015, p.355-358

2015

Link zum Volltext

Verfügbarkeit prüfen

Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

Link zum Volltext

Verfügbarkeit prüfen

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

2016 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2016, p.170-173

2016

Link zum Volltext
IEEE_Xplore

Analog performance of strained SOI nanowires down to 10K

2016 46th European Solid-State Device Research Conference (ESSDERC), 2016, p.222-225

2016

Link zum Volltext
IEEE_Xplore

An analysis of stress evolution in stacked GAA transistors

2016 IEEE Silicon Nanoelectronics Workshop (SNW), 2016, p.206-207

2016

Link zum Volltext

Verfügbarkeit prüfen

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

2022 IEEE Latin American Electron Devices Conference (LAEDC), 2022, p.1-4

2022

Link zum Volltext

Verfügbarkeit prüfen

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

Link zum Volltext

Verfügbarkeit prüfen

Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

2022 36th Symposium on Microelectronics Technology (SBMICRO), 2022, p.1-4

2022

Link zum Volltext

Verfügbarkeit prüfen

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

IEEE transactions on electron devices, 2014-04, Vol.61 (4), p.969-975

2014

Link zum Volltext
IEEE_Xplore

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

IEEE electron device letters, 2009-12, Vol.30 (12), p.1266-1268

2009

Link zum Volltext
IEEE_Xplore

Back bias impact on effective mobility of p-type nanowire SOI MOSFETs

2018 33rd Symposium on Microelectronics Technology and Devices (SBMicro), 2018, p.1-4

2018

Link zum Volltext
IEEE_Xplore

Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

2017 32nd Symposium on Microelectronics Technology and Devices (SBMicro), 2017, p.1-4

2017

Link zum Volltext

Verfügbarkeit prüfen

Benefits and challenges of FDSOI technology for 14nm node

IEEE 2011 International SOI Conference, 2011, p.1-21

Faynot, O.

2011

Link zum Volltext
IEEE_Xplore

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

IEEE electron device letters, 2013-07, Vol.34 (7), p.840-842

2013

Link zum Volltext
IEEE_Xplore

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

Link zum Volltext
IEEE_Xplore

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-03, Vol.31 (2)

2013

Link zum Volltext

Verfügbarkeit prüfen

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

IEEE electron device letters, 2012-03, Vol.33 (3), p.318-320

2012

Link zum Volltext
IEEE_Xplore

CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Proceedings of the 16th Asia and South Pacific Design Automation Conference, 2011, p.336-343

2011

Link zum Volltext

Verfügbarkeit prüfen

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits

16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011), 2011, p.336-343

2011

Link zum Volltext
IEEE_Xplore

Comparison of Device Architecture's for 0.18μm MOS Transistors on Very Thin Film SOI Material

ESSDERC '94: 24th European Solid State Device Research Conference, 1994, p.767-770

1994

Link zum Volltext
IEEE_Xplore

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

Link zum Volltext

Verfügbarkeit prüfen

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

IEEE journal of the Electron Devices Society, 2024-06, p.1-1

2024

Link zum Volltext

Verfügbarkeit prüfen

Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018, p.1-4

2018

Link zum Volltext
IEEE_Xplore

Disruptive approaches towards Energy Efficient VLSI Technologies

2023 International VLSI Symposium on Technology, Systems and Applications (VLSI-TSA/VLSI-DAT), 2023, p.1-2

2023

Link zum Volltext

Verfügbarkeit prüfen

1 – 25 von 115

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(67)
Mit Volltextzugriff
(95)

Publikationsform

Sprache

Englisch
(115)
Japanisch
(11)

Erscheinungsjahr

n.n

Thema

Science & Technology
(78)
Technology
(75)
Engineering
(73)
Engineering, Electrical & Electronic
(73)
Logic Gates
(45)
Physical Sciences
(44)
Transistors
(42)
Physics
(41)
Physics, Applied
(40)
Silicon
(35)
Electronics
(29)
Applied Sciences
(26)
Exact Sciences And Technology
(26)
Mosfet
(25)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(24)
Mosfets
(21)
Threshold Voltage
(21)
Engineering Sciences
(19)
Nanowires
(18)
Microelectronics
(16)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 90 Tagen
(2)

Menü

Weitere Dienste

Einstellungen

3D analytical modelling of subthreshold characteristics in vertical Multiple-gate FinFET transistors

4-port RF performance assessment and compact modeling of UTBB-FDSOI transistors

Analog characteristics of n-type vertically stacked nanowires

Analog performance of n- and p-FET SOI nanowires including channel length and temperature influence

Analog performance of strained SOI nanowires down to 10K

An analysis of stress evolution in stacked GAA transistors

Analysis of the Gate-Induced Drain Leakage of SOI Nanowire and Nanosheet MOS Transistors at High Temperatures

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Analysis of Variability in Transconductance and Mobility of Nanowire Transistors

Analytical Modeling of Threshold Voltage and Interface Ideality Factor of Nanoscale Ultrathin Body and Buried Oxide SOI MOSFETs With Back Gate Control

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

Back bias impact on effective mobility of p-type nanowire SOI MOSFETs

Back gate influence on transistor efficiency of SOI nMOS Ω-gate nanowire down to 10nm width

Benefits and challenges of FDSOI technology for 14nm node

Bias-Engineered Mobility in Advanced FD-SOI MOSFETs

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

CELONCEL: effective design technique for 3-D monolithic integration targeting high performance integrated circuits

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits

Comparison of Device Architecture's for 0.18μm MOS Transistors on Very Thin Film SOI Material

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Comprehensive Evaluation of Junctionless and Inversion-Mode Nanowire MOSFETs Performance at High Temperatures

Cryogenic operation of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Disruptive approaches towards Energy Efficient VLSI Technologies

Suchergebnisse filtern