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Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

IEEE transactions on nuclear science, 2013-08, Vol.60 (4), p.2583-2589

2013

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IEEE_Xplore

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

IEEE journal of the Electron Devices Society, 2023-01, Vol.11, p.1-1

2023

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On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2326-2336

2011

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IEEE_Xplore

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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IEEE_Xplore

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

IEEE electron device letters, 2012-03, Vol.33 (3), p.318-320

2012

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IEEE_Xplore

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Journal of Vacuum Science & Technology B: Microelectronics and Nanometer Structures, 2013-03, Vol.31 (2)

2013

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Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Journal of applied physics, 2011-10, Vol.110 (8), p.084901-084901-9

2011

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Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

IEEE transactions on nuclear science, 2007-12, Vol.54 (6), p.2355-2362

2007

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IEEE_Xplore

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Solid-state electronics, 2024-04, Vol.214, p.108865, Article 108865

2024

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Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Solid-state electronics, 2023-10, Vol.208, p.108716, Article 108716

2023

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Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011, Vol.58 (8), p.2473-2482

2011

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Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

2012 Symposium on VLSI Technology (VLSIT), 2012, p.113-114

2012

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IEEE_Xplore

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2473-2482

2011

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Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Solid-state electronics, 2022-08, Vol.194, p.108337, Article 108337

2022

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Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Solid-state electronics, 2023-10, Vol.208, p.108737, Article 108737

2023

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Electrical characterization of stacked SOI nanowires at low temperatures

Solid-state electronics, 2022-05, Vol.191, p.108260, Article 108260

2022

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Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

IEEE electron device letters, 2012-12, Vol.33 (12), p.1717-1719

2012

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IEEE_Xplore

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

IEEE transactions on electron devices, 2012-08, Vol.59 (8), p.2019-2026

2012

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IEEE_Xplore

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

IEEE electron device letters, 2010-03, Vol.31 (3), p.234-236

2010

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IEEE_Xplore

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

ESSDERC 2021 - IEEE 51st European Solid-State Device Research Conference (ESSDERC), 2021, p.223-226

2021

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Foreword

Solid-state electronics, 2011-05, Vol.59 (1), p.1

2011

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Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Solid-state electronics, 2019-09, Vol.159, p.83-89

2019

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Analog characteristics of n-type vertically stacked nanowires

Solid-state electronics, 2021-11, Vol.185, p.108127, Article 108127

2021

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

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IEEE_Xplore

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Impact of SOI Substrate on the Radiation Response of UltraThin Transistors Down to the 20 nm Node

High Temperature and Width Influence on the GIDL of Nanowire and Nanosheet SOI nMOSFETs

On the Variability in Planar FDSOI Technology: From MOSFETs to SRAM Cells

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Carrier-Mobility Enhancement via Strain Engineering in Future Thin-Body MOSFETs

Capped carbon hard mask and trimming process: A low-cost and efficient route to nanoscale devices

Enhanced thermal performances of silicon-on-diamond wafers incorporating ultrathin nanocrystalline diamond and silicon layers: Raman and micro-Raman analysis

Transient Radiation Response of Single- and Multiple-Gate FD SOI Transistors

Comprehensive evaluation of gate-induced drain leakage in SOI stacked nanowire nMOSFETs operating in high-temperatures

Experimental assessment of gate-induced drain leakage in SOI stacked nanowire and nanosheet nMOSFETs at high temperatures

Multi-VT UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Impact of back biasing on carrier transport in ultra-thin-body and BOX (UTBB) Fully Depleted SOI MOSFETs

Multi- V T UTBB FDSOI Device Architectures for Low-Power CMOS Circuit

Electrical characteristics of n-type vertically stacked nanowires operating up to 600 K

Impact of series resistance on the drain current variability in inversion mode and junctionless nanowire transistors

Electrical characterization of stacked SOI nanowires at low temperatures

Experimental Demonstration of Capacitorless A2RAM Cells on Silicon-on-Insulator

BSIM-IMG: A Compact Model for Ultrathin-Body SOI MOSFETs With Back-Gate Control

GeOI pMOSFETs Scaled Down to 30-nm Gate Length With Record Off-State Current

Experimental Assessment of Variability in Junctionless Nanowire nMOS Transistors

Foreword

Low temperature influence on performance and transport of Ω-gate p-type SiGe-on-insulator nanowire MOSFETs

Analog characteristics of n-type vertically stacked nanowires

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

A New Method for Series Resistance Extraction of Nanometer MOSFETs

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