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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

IEEE electron device letters, 2012-09, Vol.33 (9), p.1225-1227

2012

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Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

IEEE electron device letters, 2012-11, Vol.33 (11), p.1526-1528

2012

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Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias

IEEE transactions on electron devices, 2022-07, Vol.69 (7), p.4022-4028

2022

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Total Ionizing Dose Effects Mitigation Strategy for Nanoscaled FDSOI Technologies

IEEE transactions on nuclear science, 2014-12, Vol.61 (6), p.3023-3029

2014

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Investigations on the Geometry Effects and Bias Configuration on the TID Response of nMOS SOI Tri-Gate Nanowire Field-Effect Transistors

IEEE transactions on nuclear science, 2018-01, Vol.65 (1), p.39-45

2018

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TID Response of Nanowire Field-Effect Transistors: Impact of the Back-Gate Bias

IEEE transactions on nuclear science, 2020-10, Vol.67 (10), p.2172-2178

2020

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Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

IEEE electron device letters, 2012-09, Vol.33 (9), p.1306-1308

2012

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TID Response of pMOS Nanowire Field-Effect Transistors: Geometry and Bias Dependence

IEEE transactions on nuclear science, 2018-08, Vol.65 (8), p.1525-1531

2018

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Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

IEEE electron device letters, 2009-12, Vol.30 (12), p.1266-1268

2009

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A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

IEEE transactions on electron devices, 2007-06, Vol.54 (6), p.1366-1375

2007

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Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Semiconductor science and technology, 2019-03, Vol.34 (3), p.35003

2019

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Comparative Analysis of Mechanical Strain and Silicon Film Thickness on Charge Collection Mechanisms of Nanometer Scaled SOI Devices Under Heavy Ion and Pulsed Laser Irradiation

IEEE transactions on nuclear science, 2014-08, Vol.61 (4), p.1628-1634

2014

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Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs

IEEE transactions on electron devices, 2012-01, Vol.59 (1), p.247-251

2012

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3D monolithic integration: Technological challenges and electrical results

Microelectronic engineering, 2011-04, Vol.88 (4), p.331-335

2011

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Total Ionizing Dose Effects on Triple-Gate FETs

IEEE transactions on nuclear science, 2006-12, Vol.53 (6), p.3158-3165

2006

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Agglomeration control during the selective epitaxial growth of Si raised sources and drains on ultra-thin silicon-on-insulator substrates

Journal of crystal growth, 2005-07, Vol.280 (3), p.530-538

2005

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Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

Solid-state electronics, 2012-04, Vol.70, p.50-58

2012

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Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI)

Solid-state electronics, 2010-09, Vol.54 (9), p.861-869

2010

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Investigations on heavy ion induced Single-Event Transients (SETs) in highly-scaled FinFETs

Nuclear instruments & methods in physics research. Section B, Beam interactions with materials and atoms, 2015-12, Vol.365, p.631-635

2015

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Total ionizing dose effects on deca-nanometer fully depleted SOI devices

IEEE transactions on nuclear science, 2005-12, Vol.52 (6), p.2345-2352

2005

Volltextzugriff (PDF)

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

Solid-state electronics, 2009-07, Vol.53 (7), p.730-734

2009

Volltextzugriff (PDF)

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

IEEE transactions on nuclear science, 2013-08, Vol.60 (4), p.2590-2597

2013

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Silicon-On-Diamond layer integration by wafer bonding technology

Diamond and related materials, 2010-07, Vol.19 (7), p.796-805

2010

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Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

2016 IEEE Symposium on VLSI Technology, 2016, p.1-2

2016

Volltextzugriff (PDF)

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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

Experimental Demonstration of Ω-Gate SOI Nanowire MOS Transistors' Mobility Variation Induced by Substrate Bias

Total Ionizing Dose Effects Mitigation Strategy for Nanoscaled FDSOI Technologies

Investigations on the Geometry Effects and Bias Configuration on the TID Response of nMOS SOI Tri-Gate Nanowire Field-Effect Transistors

TID Response of Nanowire Field-Effect Transistors: Impact of the Back-Gate Bias

Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs

TID Response of pMOS Nanowire Field-Effect Transistors: Geometry and Bias Dependence

Arsenic-Segregated Rare-Earth Silicide Junctions: Reduction of Schottky Barrier and Integration in Metallic n-MOSFETs on SOI

A Model of Fringing Fields in Short-Channel Planar and Triple-Gate SOI MOSFETs

Comparison between nMOS and pMOS Ω-gate nanowire down to 10 nm width as a function of back gate bias

Comparative Analysis of Mechanical Strain and Silicon Film Thickness on Charge Collection Mechanisms of Nanometer Scaled SOI Devices Under Heavy Ion and Pulsed Laser Irradiation

Extended MASTAR Modeling of DIBL in UTB and UTBB SOI MOSFETs

3D monolithic integration: Technological challenges and electrical results

Total Ionizing Dose Effects on Triple-Gate FETs

Agglomeration control during the selective epitaxial growth of Si raised sources and drains on ultra-thin silicon-on-insulator substrates

Ultra-thin body and thin-BOX SOI CMOS technology analog figures of merit

Electrical and diffraction characterization of short and narrow MOSFETs on fully depleted strained silicon-on-insulator (sSOI)

Investigations on heavy ion induced Single-Event Transients (SETs) in highly-scaled FinFETs

Total ionizing dose effects on deca-nanometer fully depleted SOI devices

FDSOI devices with thin BOX and ground plane integration for 32 nm node and below

Investigations on the Vulnerability of Advanced CMOS Technologies to MGy Dose Environments

Silicon-On-Diamond layer integration by wafer bonding technology

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

First demonstration of a CMOS over CMOS 3D VLSI CoolCube™ integration on 300mm wafers

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