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Research and Development Priorities for Security of Embedded Hardware Devices

IEEE transactions on engineering management, 2024, Vol.71, p.2800-2811

2024

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A survey of fault tolerant methodologies for FPGAs

ACM transactions on design automation of electronic systems, 2006-04, Vol.11 (2), p.501-533

2006

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THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

IEEE transactions on circuits and systems. I, Regular papers, 2022-07, Vol.69 (7), p.2906-2915

2022

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An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.840-843

2020

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Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation

2022 IEEE 40th International Conference on Computer Design (ICCD), 2022, p.565-571

2022

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Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.820-825

2021

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Online Fault Tolerance for FPGA Logic Blocks

IEEE transactions on very large scale integration (VLSI) systems, 2007-02, Vol.15 (2), p.216-226

2007

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Online BIST and BIST-based diagnosis of FPGA logic blocks

IEEE transactions on very large scale integration (VLSI) systems, 2004-12, Vol.12 (12), p.1284-1294

2004

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Fast FPGA Reverse Engineering for Hardware Metering and Fingerprinting

NAECON 2023 - IEEE National Aerospace and Electronics Conference, 2023, p.147-151

2023

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TinyPower: Side-Channel Attacks with Tiny Neural Networks

2024 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2024, p.320-331

2024

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TripletPower: Deep-Learning Side-Channel Attacks over Few Traces

2023 IEEE International Symposium on Hardware Oriented Security and Trust (HOST), 2023, p.167-178

2023

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Critical Datapath Cells for NCL Asynchronous Circuit Area Reduction

NAECON 2021 - IEEE National Aerospace and Electronics Conference, 2021, p.400-404

2021

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An Asynchronous MPGA THx2 Cell and Architecture for Mitigating Side-Channel Attacks

2019 IEEE National Aerospace and Electronics Conference (NAECON), 2019, p.232-235

2019

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EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021, p.816-819

2021

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Determining Confidence in FPGA Bitstream Reverse Engineering Results

NAECON 2023 - IEEE National Aerospace and Electronics Conference, 2023, p.152-156

2023

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NSF CHEST IUCRC: Case Study for Leveraging NSF IUCRCs for R&D

2019 IEEE National Aerospace and Electronics Conference (NAECON), 2019, p.519-522

2019

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On Using Tabu Search for Design Automation of VLSI Systems

Journal of heuristics, 2003-01, Vol.9 (1), p.75

2003

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A Fault Tolerant Technique for FPGAs

Journal of electronic testing, 2000-12, Vol.16 (6), p.591-606

2000

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Two-dimensional Placement Using Tabu Search

VLSI Design, 2001-01, Vol.2001 (1), p.b13-23

2001

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A New Method for Testing Re-Programmable PLAs

Journal of electronic testing, 2000-12, Vol.16 (6), p.635-640

2000

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Portability of Deep-Learning Side-Channel Attacks against Software Discrepancies

Proceedings of the 16th ACM Conference on Security and Privacy in Wireless and Mobile Networks, 2023, p.227-238

2023

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Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Field-Programmable Logic and Applications, 2005, p.141-150

2005

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Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links

Proceedings of the 2023 ACM SIGSAC Conference on Computer and Communications Security, 2023, p.2024-2037

2023

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Fast floorplanning for FPGAs

Field-Programmable Logic and Applications From FPGAs to Computing Paradigm, 2006, p.129-138

2006

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A methodology for fast FPGA floorplanning

International Symposium on Field Programmable Gate Arrays: Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays; 21-23 Feb. 1999, 1999, p.47-56

1999

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Research and Development Priorities for Security of Embedded Hardware Devices

A survey of fault tolerant methodologies for FPGAs

THx2 Programmable Logic Block Architecture for Clockless Asynchronous FPGAs

An Asynchronous FPGA THx2 Programmable Cell for Mitigating Side-Channel Attacks

Area Efficient Asynchronous Circuits for Side Channel Attack Mitigation

Fully BEOL-Compatible Switch Boxes Using RRAMs and Thin Film Transistors for Reconfigurable and Secure ICs

Online Fault Tolerance for FPGA Logic Blocks

Online BIST and BIST-based diagnosis of FPGA logic blocks

Fast FPGA Reverse Engineering for Hardware Metering and Fingerprinting

TinyPower: Side-Channel Attacks with Tiny Neural Networks

TripletPower: Deep-Learning Side-Channel Attacks over Few Traces

Critical Datapath Cells for NCL Asynchronous Circuit Area Reduction

An Asynchronous MPGA THx2 Cell and Architecture for Mitigating Side-Channel Attacks

EMC: Efficient Muller C-Element Implementation for High Bit-width Asynchronous Applications

Determining Confidence in FPGA Bitstream Reverse Engineering Results

NSF CHEST IUCRC: Case Study for Leveraging NSF IUCRCs for R&D

On Using Tabu Search for Design Automation of VLSI Systems

A Fault Tolerant Technique for FPGAs

Two-dimensional Placement Using Tabu Search

A New Method for Testing Re-Programmable PLAs

Portability of Deep-Learning Side-Channel Attacks against Software Discrepancies

Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement

Gotcha! I Know What You Are Doing on the FPGA Cloud: Fingerprinting Co-Located Cloud FPGA Accelerators via Measuring Communication Links

Fast floorplanning for FPGAs

A methodology for fast FPGA floorplanning

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