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A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.126-130

2008

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Low-power direct digital frequency synthesis for wireless communications

IEEE journal of solid-state circuits, 2000-03, Vol.35 (3), p.385-390

2000

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Dynamic current mode logic (DyCML): a new low-power high-performance logic style

IEEE journal of solid-state circuits, 2001-03, Vol.36 (3), p.550-558

2001

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Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

IEEE transactions on very large scale integration (VLSI) systems, 2002-04, Vol.10 (2), p.71-78

2002

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Modeling and comparing CMOS implementations of the C-element

IEEE transactions on very large scale integration (VLSI) systems, 1998-12, Vol.6 (4), p.563-567

1998

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Modified register-exchange Viterbi decoder for low-power wireless communications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-02, Vol.51 (2), p.371-378

2004

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Fast and efficient parametric modeling of contact-to-substrate coupling

IEEE transactions on computer-aided design of integrated circuits and systems, 2000-11, Vol.19 (11), p.1282-1292

2000

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Memoryless Viterbi decoder

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-12, Vol.52 (12), p.826-830

2005

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Phase-domain fractional-N frequency synthesizers

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-03, Vol.51 (3), p.440-449

2004

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Low-power high-performance arithmetic circuits and architectures

IEEE journal of solid-state circuits, 2002-01, Vol.37 (1), p.90-94

2002

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A low-power high-performance current-mode multiport SRAM

IEEE transactions on very large scale integration (VLSI) systems, 2001-10, Vol.9 (5), p.590-598

2001

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Low-power design of decimation filters for a digital IF receiver

IEEE transactions on very large scale integration (VLSI) systems, 2000-06, Vol.8 (3), p.339-345

2000

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An electrically pre-equalized 10-Gb/s duobinary transmission system

Journal of lightwave technology, 2005-01, Vol.23 (1), p.388-400

2005

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Circuit techniques for CMOS low-power high-performance multipliers

IEEE journal of solid-state circuits, 1996-10, Vol.31 (10), p.1535-1546

1996

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Power dissipation analysis and optimization of deep submicron CMOS digital circuits

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.707-713

1996

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An electrically pre-equalized 10-Gb/s duobinary transmission system

Journal of lightwave technology, 2005-01, Vol.23 (1), p.388

2005

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TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices

IEEE transactions on computer-aided design of integrated circuits and systems, 1995-04, Vol.14 (4), p.447-458

1995

Volltextzugriff (PDF)

Area-efficient CMOS distributed amplifier using compact CMOS interconnects

Electronics letters, 2006-08, Vol.42 (17), p.970-972

2006

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A wideband sigma-delta phase-locked-loop modulator for wireless applications

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-02, Vol.50 (2), p.53-62

2003

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A fast lock digital phase-locked-loop architecture for wireless applications

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2003-02, Vol.50 (2), p.63-72

2003

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A 20-Stage CMOS Distributed Amplifier using CMOS Interconnects for Artificial Transmission Lines

2006 49th IEEE International Midwest Symposium on Circuits and Systems, 2006, Vol.2, p.194-196

2006

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A novel loss compensation technique for broadband CMOS distributed amplifiers

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-1638

2006

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A 10-GHz 15-dB Four-Stage Distributed Amplifier in 0.18 μm CMOS Process

Proceedings of the Design Automation & Test in Europe Conference, 2006, Vol.1, p.1-5

2006

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A termination technique for the averaging network of flash ADC's

2006 IEEE International Symposium on Circuits and Systems (ISCAS), 2006, p.4 pp.-3324

2006

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Leakage aware full adder cell

2007 50th Midwest Symposium on Circuits and Systems, 2007, p.968-971

2007

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A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

Low-power direct digital frequency synthesis for wireless communications

Dynamic current mode logic (DyCML): a new low-power high-performance logic style

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

Modeling and comparing CMOS implementations of the C-element

Modified register-exchange Viterbi decoder for low-power wireless communications

Fast and efficient parametric modeling of contact-to-substrate coupling

Memoryless Viterbi decoder

Phase-domain fractional-N frequency synthesizers

Low-power high-performance arithmetic circuits and architectures

A low-power high-performance current-mode multiport SRAM

Low-power design of decimation filters for a digital IF receiver

An electrically pre-equalized 10-Gb/s duobinary transmission system

Circuit techniques for CMOS low-power high-performance multipliers

Power dissipation analysis and optimization of deep submicron CMOS digital circuits

An electrically pre-equalized 10-Gb/s duobinary transmission system

TRASIM: compact and efficient two-dimensional transient simulator for arbitrary planar semiconductor devices

Area-efficient CMOS distributed amplifier using compact CMOS interconnects

A wideband sigma-delta phase-locked-loop modulator for wireless applications

A fast lock digital phase-locked-loop architecture for wireless applications

A 20-Stage CMOS Distributed Amplifier using CMOS Interconnects for Artificial Transmission Lines

A novel loss compensation technique for broadband CMOS distributed amplifiers

A 10-GHz 15-dB Four-Stage Distributed Amplifier in 0.18 μm CMOS Process

A termination technique for the averaging network of flash ADC's

Leakage aware full adder cell

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