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A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

IEEE transactions on biomedical circuits and systems, 2016-02, Vol.10 (1), p.243-254

2016

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A compact on-chip IR-drop measurement system in 28 nm CMOS technology

2014 IEEE International Symposium on Circuits and Systems (ISCAS), 2014, p.1219-1222

2014

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A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

IEEE transactions on biomedical circuits and systems, 2022-02, Vol.16 (1), p.94-107

2022

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A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2013-11, Vol.60 (11), p.741-745

2013

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Dynamic Power Management for Neuromorphic Many-Core Systems

IEEE transactions on circuits and systems. I, Regular papers, 2019-08, Vol.66 (8), p.2973-2986

2019

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Hardware Implementation of an OPC UA Server for Industrial Field Devices

IEEE transactions on very large scale integration (VLSI) systems, 2021-11, Vol.29 (11), p.1998-2002

2021

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A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2014-11, Vol.61 (11), p.835-839

2014

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A 16-Channel Fully Configurable Neural SoC With 1.52 \muW/Ch Signal Acquisition, 2.79 \muW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

IEEE transactions on biomedical circuits and systems, 2022-02, Vol.16 (1), p.94-107

2022

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A 16-Channel Fully Configurable Neural SoC With 1.52 [Formula Omitted]W/Ch Signal Acquisition, 2.79 [Formula Omitted]W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

IEEE transactions on biomedical circuits and systems, 2022-01, Vol.16 (1), p.94

2022

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An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

IEEE journal of solid-state circuits, 2015-03, Vol.50 (3), p.749-762

2015

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Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

Frontiers in neuroscience, 2015-02, Vol.9, p.10-10

2015

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A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2013-03, Vol.21 (3), p.566-570

2013

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Dynamic voltage and frequency scaling for neuromorphic many-core systems

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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A 32 GBit/s communication SoC for a waferscale neuromorphic system

Integration (Amsterdam), 2012, Vol.45 (1), p.61-75

2012

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A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

2012 IEEE International Solid-State Circuits Conference, 2012, p.180-182

2012

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A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

2012 IEEE International Symposium on Circuits and Systems (ISCAS), 2012, p.261-264

2012

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An MPSoC for energy-efficient database query processing

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

International journal of e-politics, 2012-10, Vol.3 (4), p.42-56

2012

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10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.188-189

2014

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A low-power cell-based-design multi-port register file in 65nm CMOS technology

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.313-316

2010

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Low power design of the X-GOLD® SDR 20 baseband processor

Proceedings of the Conference on Design, Automation and Test in Europe, 2010, p.792-793

2010

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Low power design of the X-GOLD® SDR 20 baseband processor

2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010), 2010, p.792-793

2010

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Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.155-158

2019

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A database accelerator for energy-efficient query processing and optimization

2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016, p.1-5

2016

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Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-1

2017

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A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

A compact on-chip IR-drop measurement system in 28 nm CMOS technology

A 16-Channel Fully Configurable Neural SoC With 1.52 μW/Ch Signal Acquisition, 2.79 μW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

Dynamic Power Management for Neuromorphic Many-Core Systems

Hardware Implementation of an OPC UA Server for Industrial Field Devices

A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology

A 16-Channel Fully Configurable Neural SoC With 1.52 \muW/Ch Signal Acquisition, 2.79 \muW/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

A 16-Channel Fully Configurable Neural SoC With 1.52 [Formula Omitted]W/Ch Signal Acquisition, 2.79 [Formula Omitted]W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

Dynamic voltage and frequency scaling for neuromorphic many-core systems

A 32 GBit/s communication SoC for a waferscale neuromorphic system

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

An MPSoC for energy-efficient database query processing

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links

10.7 A 105GOPS 36mm2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

A low-power cell-based-design multi-port register file in 65nm CMOS technology

Low power design of the X-GOLD® SDR 20 baseband processor

Low power design of the X-GOLD® SDR 20 baseband processor

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS

A database accelerator for energy-efficient query processing and optimization

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems

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