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Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

IEEE access, 2022, Vol.10, p.95571-95584

2022

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Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics

IEEE transactions on very large scale integration (VLSI) systems, 2019-04, Vol.27 (4), p.790-798

2019

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Energy Adaptive Convolution Neural Network Using Dynamic Partial Reconfiguration

2020 IEEE 63rd International Midwest Symposium on Circuits and Systems (MWSCAS), 2020, p.325-328

2020

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Traffic-Based Virtual Channel Activation for Low-Power NoC

IEEE transactions on very large scale integration (VLSI) systems, 2015-12, Vol.23 (12), p.3029-3042

2015

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Virtual Verification and Validation of Automotive System

Journal of circuits, systems, and computers, 2019-04, Vol.28 (4), p.1950071

2019

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Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design

IEEE transactions on very large scale integration (VLSI) systems, 2016-03, Vol.24 (3), p.909-919

2016

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A robust, real-time and calibration-free lane departure warning system

Microprocessors and microsystems, 2019-11, Vol.71, p.102874, Article 102874

2019

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Fast Transaction-Level Model for Direct Memory Access Controller

Journal of circuits, systems, and computers, 2019-04, Vol.28 (4), p.1950059

2019

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High Throughput Asynchronous NoC Design under High Process Variation

Integration (Amsterdam), 2015-03, Vol.49, p.1-13

2015

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FPGA-based electrocardiography (ECG) signal analysis system using least-square linear phase finite impulse response (FIR) filter

Journal of Electrical Systems and Information Technology, 2016-12, Vol.3 (3), p.513-526

2016

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CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip

Journal of parallel and distributed computing, 2019-06, Vol.128, p.151-166

2019

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PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller

Journal of parallel and distributed computing, 2020-05, Vol.139, p.135-147

2020

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INTERCONNECT MODELING WITH THE EXISTENCE OF LINE INDUCTANCE

Journal of circuits, systems, and computers, 2013-02, Vol.22 (2), p.1250082

2013

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Exponentially tapered H-tree clock distribution networks

IEEE transactions on very large scale integration (VLSI) systems, 2005-08, Vol.13 (8), p.971-975

2005

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A 90-nm CMOS Low-Energy Dual-Channel Serial/Parallel Multiplier

2019 6th International Conference on Advanced Control Circuits and Systems (ACCS) & 2019 5th International Conference on New Paradigms in Electronics & information Technology (PEIT), 2019, p.132-135

2019

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Power characteristics of inductive interconnect

IEEE transactions on very large scale integration (VLSI) systems, 2004-12, Vol.12 (12), p.1295-1306

2004

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Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Journal of parallel and distributed computing, 2017-04, Vol.102, p.175-185

2017

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Optimum wire sizing of RLC interconnect with repeaters

Integration (Amsterdam), 2004-12, Vol.38 (2), p.205-225

2004

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Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications

IEEE transactions on very large scale integration (VLSI) systems, 2017-07, Vol.25 (7), p.2144-2152

2017

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Wire shaping of RLC interconnects

Integration (Amsterdam), 2007-07, Vol.40 (4), p.461-472

2007

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Asynchronous switching for low-power networks-on-chip

Microelectronics, 2011-12, Vol.42 (12), p.1370-1379

2011

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Resistive Power in CMOS Circuits

Analog integrated circuits and signal processing, 2004-10, Vol.41 (1), p.5-11

2004

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Shielding effect of on-chip interconnect inductance

IEEE transactions on very large scale integration (VLSI) systems, 2005-03, Vol.13 (3), p.396-400

2005

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Optimization for traffic-based virtual channel activation low-power NoC

5th International Conference on Energy Aware Computing Systems & Applications, 2015, p.1-4

2015

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Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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Energy-Efficient Precision-Scaled CNN Implementation With Dynamic Partial Reconfiguration

Dual-Channel Multiplier for Piecewise-Polynomial Function Evaluation for Low-Power 3-D Graphics

Energy Adaptive Convolution Neural Network Using Dynamic Partial Reconfiguration

Traffic-Based Virtual Channel Activation for Low-Power NoC

Virtual Verification and Validation of Automotive System

Process Variation Delay and Congestion Aware Routing Algorithm for Asynchronous NoC Design

A robust, real-time and calibration-free lane departure warning system

Fast Transaction-Level Model for Direct Memory Access Controller

High Throughput Asynchronous NoC Design under High Process Variation

FPGA-based electrocardiography (ECG) signal analysis system using least-square linear phase finite impulse response (FIR) filter

CFPA: Congestion aware, fault tolerant and process variation aware adaptive routing algorithm for asynchronous Networks-on-Chip

PMSMC: Priority-based Multi-requestor Scheduler for Embedded System Memory Controller

INTERCONNECT MODELING WITH THE EXISTENCE OF LINE INDUCTANCE

Exponentially tapered H-tree clock distribution networks

A 90-nm CMOS Low-Energy Dual-Channel Serial/Parallel Multiplier

Power characteristics of inductive interconnect

Architecture level analysis for process variation in synchronous and asynchronous Networks-on-Chip

Optimum wire sizing of RLC interconnect with repeaters

Double Logarithmic Arithmetic Technique for Low-Power 3-D Graphics Applications

Wire shaping of RLC interconnects

Asynchronous switching for low-power networks-on-chip

Resistive Power in CMOS Circuits

Shielding effect of on-chip interconnect inductance

Optimization for traffic-based virtual channel activation low-power NoC

Virtual Electronic Control Unit as a Functional Mockup Unit for Heterogeneous Systems

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