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A Rugged LDMOS for LBC5 Technology

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 2005, p.327-330

2005

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High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process

IEEE transactions on electron devices, 2001-08, Vol.48 (8), p.1751-1755

2001

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SCR-LDMOS. A novel LDMOS device with ESD robustness

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094), 2000, p.341-344

2000

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Performance trade-offs and optimization of low side low voltage integrated FETs

Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting, 2004, p.160-163

2004

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Wafer chip scale packages with efficient power dissipation have small foot-print for portable applications

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 2005, p.147-150

2005

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Avalanche-induced thermal instability in Ldmos transistors

Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216), 2001, p.153-156

2001

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Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

Proceedings of the 10th International Symposium on Power Semiconductor Devices and ICs. ISPSD'98 (IEEE Cat. No.98CH36212), 1998, p.419-422

1998

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Integration of power devices in advanced mixed signal analog BiCMOS technology

Microelectronics, 2001-05, Vol.32 (5), p.409-418

Efland, T.R

2001

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Bipolar issues in advanced power BiCMOS technology

Proceedings of the 2000 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.00CH37124), 2000, p.20-27

2000

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Mild Traumatic Brain Injury : Lessons Learned from Clinical, Sports, and Combat Concussions

Rehabilitation research and practice, 2012-01, Vol.2012 (2012), p.1-5

2012

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LeadFrameOnChip offers integrated power bus and bond over active circuit

Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216), 2001, p.65-68

2001

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Peripheral motor drive PIC concerns for integrated LDMOS technologies

2004 Proceedings of the 16th International Symposium on Power Semiconductor Devices and ICs, 2004, p.159-162

2004

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Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, 2002, p.261-264

2002

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Competitive 5V-thin and 12V-thick dual gate technology isolated drain LDMOS devices

ISPSD '03. 2003 IEEE 15th International Symposium on Power Semiconductor Devices and ICs, 2003. Proceedings, 2003, p.257-260

2003

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Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications

Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, 2002, p.185-188

2002

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High-voltage drain extended MOS transistors for 0.18-mum logic CMOS process

IEEE transactions on electron devices, 2001-08, Vol.48 (8), p.1751-1755

2001

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Current status and future trends in silicon power devices

2010 International Electron Devices Meeting, 2010, p.13.1.1-13.1.4

2010

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A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

Proceedings of the 14th International Symposium on Power Semiconductor Devices and Ics, 2002, p.213-216

2002

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The optimization of LBC6 power/mixed-signal IC BiCMOS process

Proceedings of the 2001 BIPOLAR/BiCMOS Circuits and Technology Meeting (Cat. No.01CH37212), 2001, p.192-195

2001

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7 to 30V state-of-art power device implementation in 0.25μm LBC7 BiCMOS-DMOS process technology

2004

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High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process

30th European Solid-State Device Research Conference, 2000, p.376-379

2000

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VLSI CMOS fabrication modules combine with power device methods to produce 40 m/spl Omega/ and 65 m/spl Omega/, 7 V logic level P-power FETs

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings, 1996, p.71-74

1996

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Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent R/sub sp/ vs BV performance

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings, 1996, p.147-150

1996

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Multi-megahertz pulse width modulation converters with improved 1 /spl mu/m p-channel metal oxide semiconductor transistors

8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings, 1996, p.185-188

1996

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Power BiCMOS process with high voltage device implementation for 20 V mixed signal circuit applications

Proceedings of the 13th International Symposium on Power Semiconductor Devices & ICs. IPSD '01 (IEEE Cat. No.01CH37216), 2001, p.263-266

2001

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A Rugged LDMOS for LBC5 Technology

High-voltage drain extended MOS transistors for 0.18-μm logic CMOS process

SCR-LDMOS. A novel LDMOS device with ESD robustness

Performance trade-offs and optimization of low side low voltage integrated FETs

Wafer chip scale packages with efficient power dissipation have small foot-print for portable applications

Avalanche-induced thermal instability in Ldmos transistors

Analysis of high current breakdown and UIS behavior of resurf LDMOS (RLDMOS) devices

Integration of power devices in advanced mixed signal analog BiCMOS technology

Bipolar issues in advanced power BiCMOS technology

Mild Traumatic Brain Injury : Lessons Learned from Clinical, Sports, and Combat Concussions

LeadFrameOnChip offers integrated power bus and bond over active circuit

Peripheral motor drive PIC concerns for integrated LDMOS technologies

Optimization of low voltage n-channel LDMOS devices to achieve required electrical and lifetime SOA

Competitive 5V-thin and 12V-thick dual gate technology isolated drain LDMOS devices

Robust 80 V LDMOS and 100 V DECMOS in a streamlined SOI technology for analog power applications

High-voltage drain extended MOS transistors for 0.18-mum logic CMOS process

Current status and future trends in silicon power devices

A 3V to 6V in, 6A out synchronous buck PWM integrated FET switcher design uses state-of-art power IC technology

The optimization of LBC6 power/mixed-signal IC BiCMOS process

7 to 30V state-of-art power device implementation in 0.25μm LBC7 BiCMOS-DMOS process technology

High-Voltage Drain Extended MOS Transistors for 0.18 um Logic CMOS Process

VLSI CMOS fabrication modules combine with power device methods to produce 40 m/spl Omega/ and 65 m/spl Omega/, 7 V logic level P-power FETs

Self-aligned RESURF to LOCOS region LDMOS characterization shows excellent R/sub sp/ vs BV performance

Multi-megahertz pulse width modulation converters with improved 1 /spl mu/m p-channel metal oxide semiconductor transistors

Power BiCMOS process with high voltage device implementation for 20 V mixed signal circuit applications

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