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Dynamic current mode logic (DyCML): a new low-power high-performance logic style

IEEE journal of solid-state circuits, 2001-03, Vol.36 (3), p.550-558

2001

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Circuit techniques for CMOS low-power high-performance multipliers

IEEE journal of solid-state circuits, 1996-10, Vol.31 (10), p.1535-1546

1996

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Area-efficient CMOS distributed amplifier using compact CMOS interconnects

Electronics letters, 2006-08, Vol.42 (17), p.970-972

2006

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A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

IEEE transactions on circuits and systems. II, Express briefs, 2008-02, Vol.55 (2), p.126-130

2008

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Low-power direct digital frequency synthesis for wireless communications

IEEE journal of solid-state circuits, 2000-03, Vol.35 (3), p.385-390

2000

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Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

IEEE transactions on very large scale integration (VLSI) systems, 2002-04, Vol.10 (2), p.71-78

2002

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VLSI compressor design with applications to digital neural networks

IEEE transactions on very large scale integration (VLSI) systems, 1997-06, Vol.5 (2), p.230-233, Article 230

1997

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Power dissipation analysis and optimization of deep submicron CMOS digital circuits

IEEE journal of solid-state circuits, 1996-05, Vol.31 (5), p.707-713

1996

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Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects

IEEE journal of solid-state circuits, 1995-06, Vol.30 (6), p.696-700

1995

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STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits

IEEE transactions on computer-aided design of integrated circuits and systems, 1992-11, Vol.11 (11), p.1402-1417

1992

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Modeling and comparing CMOS implementations of the C-element

IEEE transactions on very large scale integration (VLSI) systems, 1998-12, Vol.6 (4), p.563-567

1998

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Modified register-exchange Viterbi decoder for low-power wireless communications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-02, Vol.51 (2), p.371-378

2004

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Global optimization approach for architectural synthesis

IEEE transactions on computer-aided design of integrated circuits and systems, 1993-09, Vol.12 (9), p.1266-1278

1993

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Memoryless Viterbi decoder

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-12, Vol.52 (12), p.826-830

2005

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Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications

IEEE journal of solid-state circuits, 1995-06, Vol.30 (6), p.691-695

1995

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Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime

IEEE journal of solid-state circuits, 1995-06, Vol.30 (6), p.629-636

1995

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Optimal synthesis of high-performance architectures

IEEE journal of solid-state circuits, 1992-03, Vol.27 (3), p.389-397

1992

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An accurate analytical propagation delay model for high-speed CML bipolar circuits

IEEE journal of solid-state circuits, 1994-01, Vol.29 (1), p.31-45

1994

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Multiemitter BiCMOS CML circuits

IEEE journal of solid-state circuits, 1992-03, Vol.27 (3), p.454-458

1992

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BiCMOS nonthreshold logic for high-speed low-power applications

IEEE journal of solid-state circuits, 1991-08, Vol.26 (8), p.1165-1167

1991

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Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

IEEE journal of solid-state circuits, 1994-06, Vol.29 (6), p.693-700

1994

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Analysis and optimization of BiCMOS digital circuit structures

IEEE journal of solid-state circuits, 1991-04, Vol.26 (4), p.676-679

1991

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Low-power BiCMOS circuits for high-speed interchip communication

IEEE journal of solid-state circuits, 1997-04, Vol.32 (4), p.604-609

1997

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Novel merged bicmos circuit structures

Electronics letters, 1990, Vol.26 (19), p.1555-1556

1990

Volltextzugriff (PDF)

Phase-domain fractional-N frequency synthesizers

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2004-03, Vol.51 (3), p.440-449

2004

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Dynamic current mode logic (DyCML): a new low-power high-performance logic style

Circuit techniques for CMOS low-power high-performance multipliers

Area-efficient CMOS distributed amplifier using compact CMOS interconnects

A Low-Noise CMOS Distributed Amplifier for Ultra-Wide-Band Applications

Low-power direct digital frequency synthesis for wireless communications

Energy-efficient noise-tolerant dynamic styles for scaled-down CMOS and MTCMOS technologies

VLSI compressor design with applications to digital neural networks

Power dissipation analysis and optimization of deep submicron CMOS digital circuits

Low-power CMOS/BiCMOS drivers and receivers for on-chip interconnects

STAIC: an interactive framework for synthesizing CMOS and BiCMOS analog circuits

Modeling and comparing CMOS implementations of the C-element

Modified register-exchange Viterbi decoder for low-power wireless communications

Global optimization approach for architectural synthesis

Memoryless Viterbi decoder

Active-pull-down nonthreshold logic BiCMOS circuits for high-speed low-power applications

Bootstrapped full-swing BiCMOS/BiNMOS logic circuits for 1.2-3.3 V supply voltage regime

Optimal synthesis of high-performance architectures

An accurate analytical propagation delay model for high-speed CML bipolar circuits

Multiemitter BiCMOS CML circuits

BiCMOS nonthreshold logic for high-speed low-power applications

Full-swing Schottky BiCMOS/BiNMOS and the effects of operating frequency and supply voltage scaling

Analysis and optimization of BiCMOS digital circuit structures

Low-power BiCMOS circuits for high-speed interchip communication

Novel merged bicmos circuit structures

Phase-domain fractional-N frequency synthesizers

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