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Modeling the temperature-dependent reverse breakdown behavior of GaAs PIN diodes

2021 International Semiconductor Conference (CAS), 2021, p.81-84

2021

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A computational method to assess the impact of urban climate on buildings using modeled climatic data

Energy and buildings, 2008, Vol.40 (3), p.215-223

2008

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Ultrafast GaAs MOVPE growth for power electronics

Journal of crystal growth, 2023-07, Vol.613, p.127201, Article 127201

2023

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Analysis and optimization of the back-gate effect on lateral high-voltage SOI devices

IEEE transactions on electron devices, 2005-07, Vol.52 (7), p.1649-1655

2005

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Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

Microelectronic engineering, 2007-11, Vol.84 (11), p.2537-2541

2007

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Thermal stability of CoSi2 layers implemented in a silicon-on-insulator substrate

Semiconductor science and technology, 2006-02, Vol.21 (2), p.157-161

2006

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Fabrication and characterization of buried silicide layers on SOI substrates for BICMOS-applications

Microelectronic engineering, 2005-12, Vol.82 (3), p.454-459

2005

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Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress

Microelectronics and reliability, 2004-09, Vol.44 (9), p.1687-1692

2004

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Different approaches to integrate patterned buried CoSi2 layers in SOI substrates

Microelectronic engineering, 2006-11, Vol.83 (11-12), p.2112-2116

2006

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Relaxed Si0.7Ge0.3 buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Thin solid films, 2000-07, Vol.369 (1-2), p.175-181

2000

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Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED)

Microelectronics and reliability, 1998-12, Vol.38 (12), p.1881-1891

1998

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Lithography-independent nanometer silicon MOSFETs on insulator

IEEE transactions on electron devices, 1996-10, Vol.43 (10), p.1626-1632

1996

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Compendium of Single Event Effects Test Results for Selected Integrated Circuits

2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS), 2020, p.1-7

2020

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Roughness improvement of the CoSi 2/Si-interface for an application as buried silicide

Microelectronic engineering, 2007, Vol.84 (11), p.2537-2541

2007

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Different approaches to integrate patterned buried CoSi 2 layers in SOI substrates

Microelectronic engineering, 2006, Vol.83 (11), p.2112-2116

2006

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Thermal stability of CoSi 2 layers implemented in a silicon-on-insulator substrate

Semiconductor science and technology, 2006-02, Vol.21 (2), p.157-161

2006

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Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 2005, p.107-110

2005

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Typical Weather Years and the Effect of Urban Microclimate on the Energy Behaviour of Buildings and HVAC Systems

Advances in building energy research, 2007-01, Vol.1 (1), p.89-103

2007

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SOA improvement of p-channel high-voltage SOI devices

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005, 2005, p.237-240

2005

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Analysis of the Back-Gate Effect on the On-State Breakdown Voltage of Smartpower SOI Devices

2006 IEEE International Reliability Physics Symposium Proceedings, 2006, p.345-351

2006

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Relaxed Si sub(0.7)Ge sub(0.3) buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Thin solid films, 2000-07, Vol.369 (1), p.175-181

2000

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Relaxed Si 0.7 Ge 0.3 buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Thin solid films, 2000-07, Vol.369 (1-2), p.175-181

2000

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Hot-carrier reliability of high side NDMOS in smart power SOI technologies

Proceedings. ISPSD '05. The 17th International Symposium on Power Semiconductor Devices and ICs, 2005, 2005, p.103-106

2005

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A new leakage mechanism in SOI smart power technologies

2005 IEEE International SOI Conference Proceedings, 2005, p.32-33

2005

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ChemInform Abstract: ASYMMETRIC REACTIONS, PART LV. ASYMMETRIC REDUCTION OF DIARYL KETONES WITH (S)‐(+)‐1‐LITHIO‐2‐METHYLPIPERIDINE

Chemischer Informationsdienst, 1978-08, Vol.9 (34)

1978

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Modeling the temperature-dependent reverse breakdown behavior of GaAs PIN diodes

A computational method to assess the impact of urban climate on buildings using modeled climatic data

Ultrafast GaAs MOVPE growth for power electronics

Analysis and optimization of the back-gate effect on lateral high-voltage SOI devices

Roughness improvement of the CoSi2/Si-interface for an application as buried silicide

Thermal stability of CoSi2 layers implemented in a silicon-on-insulator substrate

Fabrication and characterization of buried silicide layers on SOI substrates for BICMOS-applications

Transient interferometric mapping of smart power SOI ESD protection devices under TLP and vf-TLP stress

Different approaches to integrate patterned buried CoSi2 layers in SOI substrates

Relaxed Si0.7Ge0.3 buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Studies on the heat removal features of stacked SOI structures with a dedicated field solver program (SUNRED)

Lithography-independent nanometer silicon MOSFETs on insulator

Compendium of Single Event Effects Test Results for Selected Integrated Circuits

Roughness improvement of the CoSi 2/Si-interface for an application as buried silicide

Different approaches to integrate patterned buried CoSi 2 layers in SOI substrates

Thermal stability of CoSi 2 layers implemented in a silicon-on-insulator substrate

Impact of the back gate effect on bipolar junction transistors in smart power SOI technologies

Typical Weather Years and the Effect of Urban Microclimate on the Energy Behaviour of Buildings and HVAC Systems

SOA improvement of p-channel high-voltage SOI devices

Analysis of the Back-Gate Effect on the On-State Breakdown Voltage of Smartpower SOI Devices

Relaxed Si sub(0.7)Ge sub(0.3) buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Relaxed Si 0.7 Ge 0.3 buffer layers grown on patterned silicon substrates for SiGe n-channel HMOSFETs

Hot-carrier reliability of high side NDMOS in smart power SOI technologies

A new leakage mechanism in SOI smart power technologies

ChemInform Abstract: ASYMMETRIC REACTIONS, PART LV. ASYMMETRIC REDUCTION OF DIARYL KETONES WITH (S)‐(+)‐1‐LITHIO‐2‐METHYLPIPERIDINE

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