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Process integration of 20 nm electron beam lithography and nanopatterning for ultimate MOSFET device fabrication

Microelectronic engineering, 2002-07, Vol.61, p.607-612

2002

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Comparative study of calixarene and HSQ resist systems for the fabrication of sub-20 nm MOSFET device demonstrators

Microelectronic engineering, 2005-03, Vol.78, p.479-483

2005

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Influence of crystal orientation and body doping on trigate transistor performance

Solid-state electronics, 2006, Vol.50 (1), p.38-43

2006

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20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices

Microelectronic engineering, 2003-06, Vol.67, p.763-768

2003

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Realization and characterization of nano-scale FinFET devices

Microelectronic engineering, 2004-06, Vol.73-74, p.803-808

2004

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NVM based on FinFET device structures

Solid-state electronics, 2005-11, Vol.49 (11), p.1799-1804

2005

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Realization and characterization of nano-scale FinFET devices

Microelectronic engineering, 2004-06, Vol.73, p.803-808

2004

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Nanoscale FinFETs for low power applications

Solid-state electronics, 2004-10, Vol.48 (10), p.1819-1823

2004

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Comparison of Trimming Techniques for Sub-Lithographic Silicon Structures

Japanese Journal of Applied Physics, 2006-06, Vol.45 (6S), p.5552

2006

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Novel dual bit tri-gate charge trapping memory devices

IEEE electron device letters, 2004-12, Vol.25 (12), p.810-812

2004

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Comparative study of calixarene and HSQ resist systems for the fabrication of sub-20nm MOSFET device demonstrators

Microelectronic engineering, 2005-03, Vol.78-79, p.479-483

2005

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Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

Solid-state electronics, 2003-07, Vol.47 (7), p.1199-1203

2003

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Electron beam lithography for nanometer-scale planar double-gate transistors

Microelectronic engineering, 2005-03, Vol.78, p.206-211

2005

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Impact of technology parameters on device performance of UTB-SOI CMOS

Solid-state electronics, 2004-04, Vol.48 (4), p.521-527

2004

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Nanostructuring of Mo/Si multilayers by means of reactive ion etching using a three-level mask

Thin solid films, 2004-06, Vol.458 (1), p.227-232

2004

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Fabrication of ultra-thin-film SOI transistors using the recessed channel concept

Microelectronic engineering, 2005-03, Vol.78, p.224-228

2005

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Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004, 2004, p.244-245

2004

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STM writing of artificial nanostructures in ultrathin PMMA and SAM resists and subsequent pattern transfer in a Mo/Si multilayer by reactive ion etching

Applied physics. A, Materials science & processing, 1998-03, Vol.66 (7), p.S685-S688

1998

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Reactive ion etching with end point detection of microstructured Mo/Si multilayers by optical emission spectroscopy

Microelectronic engineering, 2000-12, Vol.54 (3), p.303-314

2000

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W/Si multilayers deposited by hot-filament MOCVD

Thin solid films, 1999-01, Vol.338 (1), p.70-74

1999

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Impact ionization and band-to-band tunneling in ultrathin body SOI devices with undoped channels

2003 IEEE International Conference on SOI, 2003, p.166-167

2003

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Application of Reactive Ion Etching to the Fabrication of Microstructure on Mo/Si Multilayer

Chinese physics letters, 1999-09, Vol.16 (9), p.665-666, Article 665

1999

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Planar double gate transistors with asymmetric independent gates

2005 IEEE International SOI Conference Proceedings, 2005, p.126-127

2005

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High resolution 2D Scanning Spreading Resistance Microscopy (SSRM) of thin film SOI MOSFETs with ultra short effective channel length

2003 IEEE International Conference on SOI, 2003, p.35-36

2003

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Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003, 2003, p.419-422

2003

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Process integration of 20 nm electron beam lithography and nanopatterning for ultimate MOSFET device fabrication

Comparative study of calixarene and HSQ resist systems for the fabrication of sub-20 nm MOSFET device demonstrators

Influence of crystal orientation and body doping on trigate transistor performance

20 nm electron beam lithography and reactive ion etching for the fabrication of double gate FinFET devices

Realization and characterization of nano-scale FinFET devices

NVM based on FinFET device structures

Realization and characterization of nano-scale FinFET devices

Nanoscale FinFETs for low power applications

Comparison of Trimming Techniques for Sub-Lithographic Silicon Structures

Novel dual bit tri-gate charge trapping memory devices

Comparative study of calixarene and HSQ resist systems for the fabrication of sub-20nm MOSFET device demonstrators

Design considerations for fully depleted SOI transistors in the 25–50 nm gate length regime

Electron beam lithography for nanometer-scale planar double-gate transistors

Impact of technology parameters on device performance of UTB-SOI CMOS

Nanostructuring of Mo/Si multilayers by means of reactive ion etching using a three-level mask

Fabrication of ultra-thin-film SOI transistors using the recessed channel concept

Sub-40nm tri-gate charge trapping nonvolatile memory cells for high-density applications

STM writing of artificial nanostructures in ultrathin PMMA and SAM resists and subsequent pattern transfer in a Mo/Si multilayer by reactive ion etching

Reactive ion etching with end point detection of microstructured Mo/Si multilayers by optical emission spectroscopy

W/Si multilayers deposited by hot-filament MOCVD

Impact ionization and band-to-band tunneling in ultrathin body SOI devices with undoped channels

Application of Reactive Ion Etching to the Fabrication of Microstructure on Mo/Si Multilayer

Planar double gate transistors with asymmetric independent gates

High resolution 2D Scanning Spreading Resistance Microscopy (SSRM) of thin film SOI MOSFETs with ultra short effective channel length

Drain leakage mechanisms in fully depleted SOI devices with undoped channel [MOSFETs]

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