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A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

IEEE journal of solid-state circuits, 2008-04, Vol.43 (4), p.831-843

2008

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IEEE_Xplore

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

IEEE journal of solid-state circuits, 2009-03, Vol.44 (3), p.763-774

2009

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IEEE_Xplore

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.559-565

2002

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A background optimization method for PLL by measuring phase jitter performance

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.941-950

2005

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IEEE_Xplore

Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.810-816

2012

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IEEE_Xplore

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

IEEE journal of solid-state circuits, 2010-04, Vol.45 (4), p.697-706

2010

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IEEE_Xplore

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

IEEE journal of solid-state circuits, 2012-11, Vol.47 (11), p.2773-2782

2012

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IEEE_Xplore

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers, 2013, p.272-273

2013

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IEEE_Xplore

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.404-405,405a

2009

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IEEE_Xplore

A 125a1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

IEEE journal of solid-state circuits, 2009-01, Vol.44 (3)

2009

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A 200-MHz seventh-order equiripple continuous-time filter by designof nonlinearity suppression in 0.25-mu m CMOS process

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.559-565

2002

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Verfügbarkeit prüfen

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-/spl mu/m CMOS process

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.559-565

2002

Link zum Volltext
IEEE_Xplore

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-[micro]m CMOS process

IEEE journal of solid-state circuits, 2002-05, Vol.37 (5), p.559

2002

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A background optimization method for PLL by measuring phase jitter performance

2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525), 2004, p.236-239

2004

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IEEE_Xplore

A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver

IEEE Custom Integrated Circuits Conference 2010, 2010, p.1-4

2010

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IEEE_Xplore

Visible evidence for interparticle attraction in polymer latex dispersions

Langmuir, 1985-01, Vol.1 (1), p.176-177

1985

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A flow immunoassay for alkylphenol ethoxylate surfactants and their metabolites-questions associated with cross-reactivity, matrix effects, and validation by chromatographic techniques

Analyst (London), 2003-01, Vol.128 (7), p.849-856

2003

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Recent study of polymer latex dispersions

Langmuir, 1993-02, Vol.9 (2), p.394-411

1993

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A -90dBc@10kHz phase noise fractional-N frequency synthesizer with accurate loop bandwidth control circuit

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.52-55

2005

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IEEE_Xplore

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method

2012 Symposium on VLSI Circuits (VLSIC), 2012, p.160-161

2012

Link zum Volltext
IEEE_Xplore

A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.1286-1295

2006

Link zum Volltext
IEEE_Xplore

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution

2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers, 2006, p.2422-2431

2006

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IEEE_Xplore

An over 20,000 quality factor on-chip relaxation oscillator using Power Averaging Feedback with a Chopped Amplifier

2010 Symposium on VLSI Circuits, 2010, p.111-112

2010

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IEEE_Xplore

A time-domain architecture and design method of high speed A-to-D converters with standard cells

IEEE Asian Solid-State Circuits Conference 2011, 2011, p.353-356

2011

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IEEE_Xplore

Atomic layer epitaxial growth of ZnSe, ZnTe, and ZnSe-ZnTe strained-layer superlattices

Journal of applied physics, 1989-09, Vol.66 (6), p.2597-2602

1989

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A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-μm CMOS process

A background optimization method for PLL by measuring phase jitter performance

Isolation Techniques Against Substrate Noise Coupling Utilizing Through Silicon Via (TSV) Process for RF/Mixed-Signal SoCs

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

An 11-b 300-MS/s Double-Sampling Pipelined ADC With On-Chip Digital Calibration for Memory Effects

A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR enhancement techniques utilizing noise

An on-chip CMOS relaxation oscillator with power averaging feedback using a reference proportional to supply voltage

A 125a1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

A 200-MHz seventh-order equiripple continuous-time filter by designof nonlinearity suppression in 0.25-mu m CMOS process

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-/spl mu/m CMOS process

A 200-MHz seventh-order equiripple continuous-time filter by design of nonlinearity suppression in 0.25-[micro]m CMOS process

A background optimization method for PLL by measuring phase jitter performance

A 69.8 dB SNDR 3rd-order Continuous Time Delta-Sigma Modulator with an Ultimate Low Power Tuning System for a Worldwide Digital TV-Receiver

Visible evidence for interparticle attraction in polymer latex dispersions

A flow immunoassay for alkylphenol ethoxylate surfactants and their metabolites-questions associated with cross-reactivity, matrix effects, and validation by chromatographic techniques

Recent study of polymer latex dispersions

A -90dBc@10kHz phase noise fractional-N frequency synthesizer with accurate loop bandwidth control circuit

A 10 MHz BW 50 fJ/conv. continuous time ΔΣ modulator with high-order single opamp integrator using optimization-based design method

A 0.03mm/sup 2/ 9mW Wide-Range Duty-CycleCorrecting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR Interface

A PLL for a DVD-16 Write System with 63 Output Phases and 32ps Resolution

An over 20,000 quality factor on-chip relaxation oscillator using Power Averaging Feedback with a Chopped Amplifier

A time-domain architecture and design method of high speed A-to-D converters with standard cells

Atomic layer epitaxial growth of ZnSe, ZnTe, and ZnSe-ZnTe strained-layer superlattices

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