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Junctionless Multiple-Gate Transistors for Analog Applications

IEEE transactions on electron devices, 2011-08, Vol.58 (8), p.2511-2519

2011

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Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2012-12, Vol.59 (12), p.3510-3518

2012

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Analysis of the leakage current in junctionless nanowire transistors

Applied physics letters, 2013-11, Vol.103 (20)

2013

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Cross-coupling effects in common-source current mirrors composed by UTBB transistors

Solid-state electronics, 2022-08, Vol.194, p.108352, Article 108352

2022

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Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2014-05, Vol.61 (5), p.1575-1582

2014

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Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates

Solid-state electronics, 2013-12, Vol.90, p.121-126

2013

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A New Method for Series Resistance Extraction of Nanometer MOSFETs

IEEE transactions on electron devices, 2017-07, Vol.64 (7), p.2797-2803

2017

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A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Solid-state electronics, 2013-12, Vol.90, p.12-17

2013

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Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2016-02, Vol.63 (2), p.856-863

2016

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Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors

IEEE journal of the Electron Devices Society, 2023, Vol.11, p.634-641

2023

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The zero temperature coefficient in junctionless nanowire transistors

Applied physics letters, 2012-08, Vol.101 (6), p.62101

2012

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Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

Solid-state electronics, 2011-08, Vol.62 (1), p.99-105

2011

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Threshold voltage in junctionless nanowire transistors

Semiconductor science and technology, 2011-10, Vol.26 (10), p.105009-2

2011

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Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Microelectronic engineering, 2019-07, Vol.215, p.111005, Article 111005

2019

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Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

IEEE transactions on electron devices, 2020-06, Vol.67 (6), p.2536-2543, Article 2536

2020

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Static and dynamic compact analytical model for junctionless nanowire transistors

Journal of physics. Condensed matter, 2018-08, Vol.30 (33), p.334002-334002

2018

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Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs

Journal of Integrated Circuits and Systems, 2021-08, Vol.16 (2), p.1-7

2021

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Junctionless nanowire transistors operation at temperatures down to 4.2 K

Semiconductor science and technology, 2016-10, Vol.31 (11), p.114001

2016

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UTBB Thermal Coupling Analysis in Technological Node Level

Journal of Integrated Circuits and Systems, 2020-07, Vol.15 (2), p.1-5

2020

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On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

Solid-state electronics, 2016-03, Vol.117, p.152-160

2016

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Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Microelectronic engineering, 2017-06, Vol.178, p.17-20

2017

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Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

Journal of Integrated Circuits and Systems, 2020-05, Vol.15 (1), p.1-6

2020

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Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

Solid-state electronics, 2019-09, Vol.159, p.116-122

2019

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Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Microelectronic engineering, 2015-11, Vol.147, p.23-26

2015

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Errata to "Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors" [Dec 12 3510-3518]

IEEE transactions on electron devices, 2016-01, Vol.63 (1), p.527-527

2016

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Junctionless Multiple-Gate Transistors for Analog Applications

Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors

Analysis of the leakage current in junctionless nanowire transistors

Cross-coupling effects in common-source current mirrors composed by UTBB transistors

Substrate Bias Influence on the Operation of Junctionless Nanowire Transistors

Low-frequency noise of n-type triple gate FinFETs fabricated on standard and 45° rotated substrates

A New Method for Series Resistance Extraction of Nanometer MOSFETs

A physically-based threshold voltage definition, extraction and analytical model for junctionless nanowire transistors

Analytical Model for the Dynamic Behavior of Triple-Gate Junctionless Nanowire Transistors

Analysis of Standard-MOS and Ultra-Low-Power Diodes Composed by SOI UTBB Transistors

The zero temperature coefficient in junctionless nanowire transistors

Harmonic distortion of 2-MOS structures for MOSFET-C filters implemented with n-type unstrained and strained FINFETS

Threshold voltage in junctionless nanowire transistors

Modeling the interface traps-related low frequency noise in triple-gate SOI junctionless nanowire transistors

Analytical Model for Low-Frequency Noise in Junctionless Nanowire Transistors

Static and dynamic compact analytical model for junctionless nanowire transistors

Effect of Substrate Bias and Temperature Variation in the Capacitive Coupling of SOI UTBB MOSFETs

Junctionless nanowire transistors operation at temperatures down to 4.2 K

UTBB Thermal Coupling Analysis in Technological Node Level

On the improvement of DC analog characteristics of FD SOI transistors by using asymmetric self-cascode configuration

Analysis of the substrate bias effect on the interface trapped charges in junctionless nanowire transistors through low-frequency noise characterization

Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

Compact modeling of triple gate junctionless MOSFETs for accurate circuit design in a wide temperature range

Extraction of the interface trap density energetic distribution in SOI Junctionless Nanowire Transistors

Errata to "Surface-Potential-Based Drain Current Analytical Model for Triple-Gate Junctionless Nanowire Transistors" [Dec 12 3510-3518]

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