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A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.19-26

2020

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A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1214-1226

2018

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A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

IEEE journal of solid-state circuits, 2023-04, Vol.58 (4), p.1074-1086

2023

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Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

IEEE journal of solid-state circuits, 2020-04, Vol.55 (4), p.1124-1124

2020

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A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.3220-3231

2012

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A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2009-04, Vol.44 (4), p.1298-1305

2009

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30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

IEEE transactions on microwave theory and techniques, 2005-01, Vol.53 (1), p.123-133

2005

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The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1830-1845

2006

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An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

IEEE journal of solid-state circuits, 2012-04, Vol.47 (4), p.884-896

2012

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A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1744-1755

2016

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A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

IEEE journal of solid-state circuits, 2005-04, Vol.40 (4), p.994-1003

2005

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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

IEEE journal of solid-state circuits, 2007-10, Vol.42 (10), p.2077-2085

2007

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A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3526-3538

2009

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A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1\mathrm} Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2024, p.1-2

2024

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On-chip antennas in silicon ICs and their application

IEEE transactions on electron devices, 2005-07, Vol.52 (7), p.1312-1323

2005

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6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.122-124

2019

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A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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A 1.8 pJ/bit [Formula Omitted] Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1744

2016

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6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017, p.118-119

2017

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A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

IEEE journal of solid-state circuits, 2015-08, Vol.50 (8), p.1917-1931

2015

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A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.182-183,183a

2009

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A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers, 2009, p.368-369,369a

2009

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A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014, p.1-4

2014

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Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

2006 IEEE Compound Semiconductor Integrated Circuit Symposium, 2006, p.235-238

2006

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On-Chip Antenna Test Structure Design with Reduced Sensitivity to Probe Pad Effects

2018 IEEE International Symposium on Antennas and Propagation & USNC/URSI National Radio Science Meeting, 2018, p.361-362

2018

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A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS

A 32 Gb/s, 4.7 pJ/bit Optical Link With −11.7 dBm Sensitivity in 14-nm FinFET CMOS

A 72-GS/s, 8-Bit DAC-Based Wireline Transmitter in 4-nm FinFET CMOS for 200+ Gb/s Serial Links

Errata - Erratum to "A 128-Gb/s 1.3-pJ/b PAM-4 Transmitter With Reconfigurable 3-Tap FFE in 14-nm CMOS"

A 19-Gb/s Serial Link Receiver With Both 4-Tap FFE and 5-Tap DFE Functions in 45-nm SOI CMOS

A 12-Gb/s 11-mW Half-Rate Sampled 5-Tap Decision Feedback Equalizer With Current-Integrating Summers in 45-nm SOI CMOS Technology

30-100-GHz inductors and transformers for millimeter-wave (Bi)CMOS integrated circuits

The Invariance of Characteristic Current Densities in Nanoscale MOSFETs and Its Impact on Algorithmic Design Methodologies and Design Porting of Si(Ge) (Bi)CMOS High-Speed Building Blocks

An 8x 10-Gb/s Source-Synchronous I/O System Based on High-Density Silicon Carrier Interconnects

A 1.8 pJ/bit 16 \times 16\;\text Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

A 2.5-V 45-Gb/s decision circuit using SiGe BiCMOS logic

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

A 10-Gb/s Compact Low-Power Serial I/O With DFE-IIR Equalization in 65-nm CMOS

A 0.88pJ/bit 112Gb/s PAM4 Transmitter with 1\mathrm} Output Swing and 5-Tap Analog FFE in 7nm FinFET CMOS

On-chip antennas in silicon ICs and their application

6.6 A 128Gb/s 1.3pJ/b PAM-4 Transmitter with Reconfigurable 3-Tap FFE in 14nm CMOS

A 1.4 pJ/bit, Power-Scalable 16×12 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A 1.8 pJ/bit [Formula Omitted] Source-Synchronous Parallel Interface in 32 nm SOI CMOS with Receiver Redundancy for Link Recalibration

6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOS

A 1.4 pJ/bit, Power-Scalable 1612 Gb/s Source-Synchronous I/O With DFE Receiver in 32 nm SOI CMOS Technology

A 10Gb/s compact low-power serial I/O with DFE-IIR equalization in 65nm CMOS

A 78mW 11.1Gb/s 5-tap DFE receiver with digitally calibrated current-integrating summers in 65nm CMOS

A 1.4-pJ/b, power-scalable 16×12-Gb/s source-synchronous I/O with DFE receiver in 32nm SOI CMOS technology

Low-Power Circuits for a 2.5-V, 10.7-to-86-Gb/s Serial Transmitter in 130-nm SiGe BiCMOS

On-Chip Antenna Test Structure Design with Reduced Sensitivity to Probe Pad Effects

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