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A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.759-771

2006

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Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

2015 IEEE Custom Integrated Circuits Conference (CICC), 2015, p.1-3

2015

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Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1692-1706

2006

Volltextzugriff (PDF)

Power-conscious design of the Cell processor's synergistic processor element

IEEE MICRO, 2005-09, Vol.25 (5), p.10-18

2005

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Designing for a gigahertz [guTS integer processor]

IEEE MICRO, 1998-05, Vol.18 (3), p.66-74

1998

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The microarchitecture of the synergistic processor for a cell processor

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.63-70

2006

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Prospective for nanowire transistors

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013, p.1-8

2013

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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

IEEE MICRO, 2005-09, Vol.25 (5), p.30-38

2005

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Recent advances in ASIC-compatible circuit techniques for a SOC in newly emerging application areas: Invited paper

2014 International SoC Design Conference (ISOCC), 2014, p.24-25

2014

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A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.486-612 Vol. 1

2005

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1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673-1679

2000

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1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673

2000

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Designing for a gigahertz - guTS integer processor

IEEE MICRO, 1998-05, Vol.18 (3), p.66-74

1998

Volltextzugriff (PDF)

A variable precharge voltage sensing

IEEE journal of solid-state circuits, 1995-01, Vol.30 (1), p.25-28

1995

Volltextzugriff (PDF)

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

IEEE transactions on electron devices, 1986-03, Vol.33 (3), p.345-353

1986

Volltextzugriff (PDF)

A method to measure impedance of chip/package/board power supply system using pseudo-impulse current

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.33-36

2006

Volltextzugriff (PDF)

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

1989

Volltextzugriff (PDF)

Power supply noise simulation considering dynamic effect of on-chip current

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.87-90

2006

Volltextzugriff (PDF)

Minimum-width control-current pulse for Josephson logic gates

IEEE transactions on electron devices, 1980-10, Vol.27 (10), p.1965-1973

1980

Volltextzugriff (PDF)

A Josephson dc-powered latch

Applied physics letters, 1981-06, Vol.38 (11), p.936-938

1981

Volltextzugriff (PDF)

Corrections to "Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

IEEE transactions on electron devices, 1986-07, Vol.33 (7), p.1079-1079

1986

Volltextzugriff (PDF)

A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.24-27

2005

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The Power Conscious Synergistic Processor Element of a Cell Processor

2005 IEEE Asian Solid-State Circuits Conference, 2005, p.21-24

2005

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A high performance sensing scheme for CMOS DRAMs

1987 Symposium on VLSI Circuits, 1987, p.83-84

1987

Volltextzugriff (PDF)

Clinical implications of serum galactomannan measurement in patients with acute invasive fungal rhinosinusitis

Rhinology, 2016-12, Vol.54 (4), p.336-341

2016

Volltextzugriff (PDF)

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A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

Custom 6-R, 2- or 4-W multi-port register files in an ASIC SOC with a DVFS window of 0.5 V, 130 MHz to 0.96 V, 3.2 GHz in a 28-nm HKMG CMOS technology

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

Power-conscious design of the Cell processor's synergistic processor element

Designing for a gigahertz [guTS integer processor]

The microarchitecture of the synergistic processor for a cell processor

Prospective for nanowire transistors

Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

Recent advances in ASIC-compatible circuit techniques for a SOC in newly emerging application areas: Invited paper

A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

1-GHz fully pipelined 3.7-ns address access time 8 k x 1024 embedded synchronous DRAM macro

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

Designing for a gigahertz - guTS integer processor

A variable precharge voltage sensing

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

A method to measure impedance of chip/package/board power supply system using pseudo-impulse current

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

Power supply noise simulation considering dynamic effect of on-chip current

Minimum-width control-current pulse for Josephson logic gates

A Josephson dc-powered latch

Corrections to "Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

A fully-pipelined single-precision floating point unit in the synergistic processor element of a CELL processor

The Power Conscious Synergistic Processor Element of a Cell Processor

A high performance sensing scheme for CMOS DRAMs

Clinical implications of serum galactomannan measurement in patients with acute invasive fungal rhinosinusitis

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