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The microarchitecture of the synergistic processor for a cell processor

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.63-70

2006

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A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

IEEE journal of solid-state circuits, 2006-04, Vol.41 (4), p.759-771

2006

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Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

IEEE journal of solid-state circuits, 2006-08, Vol.41 (8), p.1692-1706

2006

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Cell Broadband Engine Processor Design Methodology

2007 IEEE Custom Integrated Circuits Conference, 2007, p.711-716

2007

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Power-conscious design of the Cell processor's synergistic processor element

IEEE MICRO, 2005-09, Vol.25 (5), p.10-18

2005

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A streaming processing unit for a CELL processor

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.134-135 Vol. 1

2005

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Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

IEEE MICRO, 2005-09, Vol.25 (5), p.30-38

2005

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A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.486-612 Vol. 1

2005

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The vector floating-point unit in a synergistic processor element of a CELL processor

17th IEEE Symposium on Computer Arithmetic (ARITH'05), 2005, p.59-67

2005

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Minimum-width control-current pulse for Josephson logic gates

IEEE transactions on electron devices, 1980-10, Vol.27 (10), p.1965-1973

1980

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1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673

2000

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1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

IEEE journal of solid-state circuits, 2000-11, Vol.35 (11), p.1673-1679

2000

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A large V/sub DS/ data retention test pattern for DRAM's

IEEE journal of solid-state circuits, 1992-08, Vol.27 (8), p.1214-1217

1992

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A variable precharge voltage sensing

IEEE journal of solid-state circuits, 1995-01, Vol.30 (1), p.25-28

1995

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A pulsed sensing scheme with a limited bit-line swing

IEEE journal of solid-state circuits, 1992-04, Vol.27 (4), p.678-682

1992

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A method to measure impedance of chip/package/board power supply system using pseudo-impulse current

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.33-36

2006

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Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

IEEE transactions on electron devices, 1986-03, Vol.33 (3), p.345-353

1986

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A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

IEEE journal of solid-state circuits, 1989-10, Vol.24 (5), p.1198-1205

1989

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A 14-ns 14-Mb CMOS DRAM with 300-mW active power

IEEE journal of solid-state circuits, 1992-09, Vol.27 (9), p.1222-1228

1992

Volltextzugriff (PDF)

The circuits and physical design of the synergistic processor element of a CELL processor

Digest of Technical Papers. 2005 Symposium on VLSI Circuits, 2005, 2005, p.20-23

2005

Volltextzugriff (PDF)

Power supply noise simulation considering dynamic effect of on-chip current

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.87-90

2006

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High-speed sensing scheme for CMOS DRAMs

IEEE journal of solid-state circuits, 1988-02, Vol.23 (1), p.34-40

1988

Volltextzugriff (PDF)

A Josephson dc-powered latch

Applied physics letters, 1981-06, Vol.38 (11), p.936-938

1981

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Corrections to "Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

IEEE transactions on electron devices, 1986-07, Vol.33 (7), p.1079-1079

1986

Volltextzugriff (PDF)

The circuit design of the synergistic processor element of a CELL processor

ICCAD-2005. IEEE/ACM International Conference on Computer-Aided Design, 2005, 2005, p.111-117

2005

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The microarchitecture of the synergistic processor for a cell processor

A fully pipelined single-precision floating-point unit in the synergistic processor element of a CELL processor

Circuit Design Techniques for a First-Generation Cell Broadband Engine Processor

Cell Broadband Engine Processor Design Methodology

Power-conscious design of the Cell processor's synergistic processor element

A streaming processing unit for a CELL processor

Low-power design approach of 11FO4 256-Kbyte embedded SRAM for the synergistic processor element of a Cell processor

A 4.8GHz fully pipelined embedded SRAM in the streaming processor of a CELL processor

The vector floating-point unit in a synergistic processor element of a CELL processor

Minimum-width control-current pulse for Josephson logic gates

1-GHz fully pipelined 3.7-ns address access time 8 k×1024 embedded synchronous DRAM macro

1-GHz fully pipelined 3.7-ns address access time 8 k/spl times/1024 embedded synchronous DRAM macro

A large V/sub DS/ data retention test pattern for DRAM's

A variable precharge voltage sensing

A pulsed sensing scheme with a limited bit-line swing

A method to measure impedance of chip/package/board power supply system using pseudo-impulse current

Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

A 22-ns 1-Mbit CMOS high-speed DRAM with address multiplexing

A 14-ns 14-Mb CMOS DRAM with 300-mW active power

The circuits and physical design of the synergistic processor element of a CELL processor

Power supply noise simulation considering dynamic effect of on-chip current

High-speed sensing scheme for CMOS DRAMs

A Josephson dc-powered latch

Corrections to "Design and characteristics of a lightly doped drain (LDD) device fabricated with self-aligned titanium disilicide

The circuit design of the synergistic processor element of a CELL processor

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