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Novel Moving Coprime Array Configurations for Real-Valued Sources

IEEE signal processing letters, 2022, Vol.29, p.657-661

2022

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A Novel Nested Array for Real-Valued Sources Exploiting Array Motion

IEEE signal processing letters, 2021, Vol.28, p.1375-1379

2021

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FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation

2024 37th International Conference on VLSI Design and 2024 23rd International Conference on Embedded Systems (VLSID), 2024, p.617-622

2024

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Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification

IEEE transactions on very large scale integration (VLSI) systems, 2018-09, Vol.26 (9), p.1750-1762

2018

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CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

Circuits, systems, and signal processing, 2018-11, Vol.37 (11), p.5101-5126

2018

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CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism

Journal of signal processing systems, 2019-05, Vol.91 (5), p.539-550

2019

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Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise

IEEE transactions on very large scale integration (VLSI) systems, 2019-05, Vol.27 (5), p.1223-1227

2019

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SIBAM-Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications

IEEE transactions on circuits and systems. II, Express briefs, 2020-11, Vol.67 (11), p.2702-2706

2020

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On Fast and Exact Computation of Error Metrics in Approximate LSB Adders

IEEE transactions on very large scale integration (VLSI) systems, 2020-04, Vol.28 (4), p.876-889

2020

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ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design

IEEE transactions on emerging topics in computing, 2022-10, Vol.10 (4), p.2072-2078

2022

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Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method

Circuits, systems, and signal processing, 2018-12, Vol.37 (12), p.5595-5615

2018

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An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform

Journal of signal processing systems, 2018-11, Vol.90 (11), p.1569-1580

2018

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Novel architecture for measurements in resistive MEMS sensors

Measurement science & technology, 2014-05, Vol.25 (5), p.55106

2014

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Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support

Journal of parallel and distributed computing, 2021-05, Vol.151, p.13-23

2021

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A Novel k-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom

IEEE signal processing letters, 2022, Vol.29, p.1402-1406

2022

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Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies

Journal of parallel and distributed computing, 2019-08, Vol.130, p.110-125

2019

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A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom

Circuits, systems, and signal processing, 2024-09, Vol.43 (9), p.6023-6034

2024

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A Novel [Formula Omitted]-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom

IEEE signal processing letters, 2022-01, Vol.29, p.1402

2022

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FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion

Journal of parallel and distributed computing, 2022-09, Vol.167, p.50-63

2022

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Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling

Circuits, systems, and signal processing, 2023-12, Vol.42 (12), p.7275-7296

2023

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A special coprime array configuration for increased degrees of freedom

Digital signal processing, 2022-04, Vol.122, p.103369, Article 103369

2022

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Optimal Coprime Array: Properties, Optimization, and k-times extension

Circuits, systems, and signal processing, 2023-06, Vol.42 (6), p.3770-3794

2023

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A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation

Circuits, systems, and signal processing, 2023-04, Vol.42 (4), p.2494-2505

2023

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An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom

Circuits, systems, and signal processing, 2023-03, Vol.42 (3), p.1860-1872

2023

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A Novel Method for Placing the Sensors for Noncircular Sources in DOA Estimation to Reduce the Mutual Coupling

2023 3rd International Conference on Range Technology (ICORT), 2023, p.1-5

2023

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Novel Moving Coprime Array Configurations for Real-Valued Sources

A Novel Nested Array for Real-Valued Sources Exploiting Array Motion

FPGA Specific Speed-Area Optimized Architectures of Arithmetic Cores with Scan Insertion for Carry Chain Based Multi-level Logic Implementation

Algorithm and VLSI Architecture Design of Proportionate-Type LMS Adaptive Filters for Sparse System Identification

CORDIC-Based High Throughput Sliding DFT Architecture with Reduced Error-Accumulation

CORDIC-Based VLSI Architectures of Running DFT with Refreshing Mechanism

Robust Proportionate Adaptive Filter Architectures Under Impulsive Noise

SIBAM-Sign Inclusive Broken Array Multiplier Design for Error Tolerant Applications

On Fast and Exact Computation of Error Metrics in Approximate LSB Adders

ACBAM-Accuracy-Configurable Sign Inclusive Broken Array Booth Multiplier Design

Reliable VLSI Architecture Design Using Modulo-Quad-Transistor Redundancy Method

An Efficient VLSI Architecture for Computation of Discrete Fractional Fourier Transform

Novel architecture for measurements in resistive MEMS sensors

Speed-area optimized VLSI architecture of multi-bit cellular automaton cell based random number generator on FPGA with testable logic support

A Novel k-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom

Design and automation of VLSI architectures for bidirectional scan based fault localization approach in FPGA fabric aware cellular automata topologies

A Generalized Rearranged Coprime Array Configuration for Direction-of-Arrival Estimation with Increased Degrees of Freedom

A Novel [Formula Omitted]-times Extended Coprime Array for DOA Estimation With Increased Degrees of Freedom

FPGA fabric conscious architecture design and automation of speed-area efficient Margolus neighborhood based cellular automata with variegated scan path insertion

Unfolded Coprime Transformed Nested Arrays for Increased DOF and Negligible Mutual Coupling

A special coprime array configuration for increased degrees of freedom

Optimal Coprime Array: Properties, Optimization, and k-times extension

A Novel Translated Coprime Array Configuration for Moving Platform in Direction-of-Arrival Estimation

An Improved CACIS Configuration for DOA Estimation with Enhanced Degrees of Freedom

A Novel Method for Placing the Sensors for Noncircular Sources in DOA Estimation to Reduce the Mutual Coupling

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