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Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

IEEE transactions on nuclear science, 2011-10, Vol.58 (5), p.2161-2168

2011

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Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging

IEEE transactions on nuclear science, 2010-06, Vol.57 (3), p.1063-1070

2010

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Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

IEEE transactions on instrumentation and measurement, 2011-06, Vol.60 (6), p.1942-1951

2011

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A High Load Current, Low-Noise, Area-Efficient, Full On-Chip Regulator for CMOS Pixel Sensors

IEEE transactions on nuclear science, 2012-06, Vol.59 (3), p.582-588

2012

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Integrating internet of things and mixed reality to teach performance-based architectural design: a case study of shading devices

Education and information technologies, 2022-08, Vol.27 (7), p.9125-9143

2022

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Formal verification of mixed-signal circuits using extended PSL

2009 IEEE 8th International Conference on ASIC, 2009, p.1288-1293

2009

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An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

Journal of semiconductors, 2009-09, Vol.30 (9), p.129-134

郑然魏廷存王佳高德远

2009

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A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors

2009 IEEE International Workshop on Imaging Systems and Techniques, 2009, p.183-186

2009

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A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2013-02, Vol.701, p.37-43

2013

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Network on Chip for Parallel DSP Architectures

Embedded Software and Systems, 2005, p.265-274

2005

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Verifying Dynamics of Mixed-signal Circuits with Random Noise using Statistical Petri Net

2007 7th International Conference on ASIC, 2007, p.1209-1212

2007

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A full on-chip, low noise, low power consumption reference generator in monolithic active pixel sensors

Nuclear instruments & methods in physics research. Section A, Accelerators, spectrometers, detectors and associated equipment, 2011-12, Vol.659 (1), p.98-105

2011

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Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip

Embedded Software and Systems, 2005, p.299-309

2005

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Adaptive Low-Power Transmission Coding for Serial Links in Network-on-Chip

Procedia engineering, 2012, Vol.29, p.1618-1624

2012

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Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation

2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors, 2013, p.346-355

2013

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Three-Operand Floating-Point Adder

2012 IEEE 12th International Conference on Computer and Information Technology, 2012, p.192-196

2012

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A multi-path fused add-subtract unit for Digital Signal Processing

2012 IEEE International Conference on Computer Science and Automation Engineering (CSAE), 2012, Vol.3, p.448-452

2012

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Advances in front-end readout ASIC design for PET imaging

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012, p.1-4

2012

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Dual-path architecture of floating-point dot product computation

Proceedings of 2011 International Conference on Computer Science and Network Technology, 2011, Vol.4, p.2272-2276

2011

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Improved Morphological TOP-HAT Filter Optimized with Genetic Algorithm

2009 2nd International Congress on Image and Signal Processing, 2009, p.1-5

2009

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A novel concurrent error detection circuit for Leading Zero Anticipator

2010 2nd International Conference on Computer Engineering and Technology, 2010, Vol.6, p.V6-440-V6-443

2010

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Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router

2012 IEEE 12th International Conference on Computer and Information Technology, 2012, p.700-705

2012

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A survey on cache coherence for tiled many-core processor

2012 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2012), 2012, p.114-118

2012

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Breakpoint debugging mechanism for microprocessor design

ASIC, 2003. Proceedings. 5th International Conference on, 2003, Vol.1, p.456-458 Vol.1

2003

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An evaluation of the many-core Longtium SP computer system

2013 IEEE International Conference on Signal Processing, Communication and Computing (ICSPCC 2013), 2013, p.1-4

2013

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Design and Characteristics of an Integrated Multichannel Ramp ADC Using Digital DLL Techniques for Small Animal PET Imaging

Precise Multiphase Clock Generation Using Low-Jitter Delay-Locked Loop Techniques for Positron Emission Tomography Imaging

Design of a 12-Bit 2.5 MS/s Integrated Multi-Channel Single-Ramp Analog-to-Digital Converter for Imaging Detector Systems

A High Load Current, Low-Noise, Area-Efficient, Full On-Chip Regulator for CMOS Pixel Sensors

Integrating internet of things and mixed reality to teach performance-based architectural design: a case study of shading devices

Formal verification of mixed-signal circuits using extended PSL

An area-saving and high power efficiency charge pump built in a TFT-LCD driver IC

A 12-bit 2.5MS/s multi-channel ramp Analog-to-Digital Converter for Imaging detectors

A built-in SRAM for radiation hard CMOS pixel sensors dedicated to high energy physics experiments

Network on Chip for Parallel DSP Architectures

Verifying Dynamics of Mixed-signal Circuits with Random Noise using Statistical Petri Net

A full on-chip, low noise, low power consumption reference generator in monolithic active pixel sensors

Microprocessor Based Self Schedule and Parallel BIST for System-On-a-Chip

Adaptive Low-Power Transmission Coding for Serial Links in Network-on-Chip

Correctly rounded architectures for Floating-Point multi-operand addition and dot-product computation

Three-Operand Floating-Point Adder

A multi-path fused add-subtract unit for Digital Signal Processing

Advances in front-end readout ASIC design for PET imaging

Dual-path architecture of floating-point dot product computation

Improved Morphological TOP-HAT Filter Optimized with Genetic Algorithm

A novel concurrent error detection circuit for Leading Zero Anticipator

Modeling and Performance Analysis of Network on Chip Based on Improved Asymmetric Multi-channel Router

A survey on cache coherence for tiled many-core processor

Breakpoint debugging mechanism for microprocessor design

An evaluation of the many-core Longtium SP computer system

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