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Seasonal prediction of Horn of Africa long rains using machine learning: The pitfalls of preselecting correlated predictors

Frontiers in water, 2022-12, Vol.4

2022

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Dosing of piperacillin/tazobactam in a morbidly obese patient

Journal of antimicrobial chemotherapy, 2012-03, Vol.67 (3), p.782-783

2012

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Comparison of Allergen-Induced Late Inflammatory Reactions in the Nose and in the Skin in House Dust Mite-Allergic Patients with or without Asthma

International archives of allergy and immunology, 2003-04, Vol.130 (4), p.266-274

2003

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A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

IEEE transactions on very large scale integration (VLSI) systems, 2002-08, Vol.10 (4), p.515-518

2002

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Evolution of substrate noise generation mechanisms with CMOS technology scaling

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-02, Vol.53 (2), p.296-305

2006

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Beyond the horizon: The next 10x reduction in power - Challenges and solutions

2011 IEEE International Solid-State Circuits Conference, 2011, p.31-31

2011

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Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-06, Vol.25 (6), p.1146-1154

2006

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A linear threshold gate implementation in single electron technology

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.93-98

2001

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Energy-efficient link layer for wireless microsensor networks

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.16-21

2001

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Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors

Journal of VLSI signal processing, 2004-05, Vol.37 (1), p.53-73

2004

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Transport equations in heavy doped silicon

IEEE transactions on electron devices, 1973-03, Vol.20 (3), p.290-298

1973

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A 1-GSPS CMOS flash A/D converter for system-on-chip applications

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.135-139

2001

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SITCAP -- A simulator of bipolar transistors for computer-aided circuit analysis programs

1973 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1973, Vol.XVI, p.104-105

1973

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A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461), 1999, p.261-270

1999

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Background memory area estimation for multidimensional signal processing systems

IEEE transactions on very large scale integration (VLSI) systems, 1995-06, Vol.3 (2), p.157-172

1995

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A novel architecture for low-power design of parallel multipliers

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.149-154

2001

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Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors

Proceedings IEEE Alessandro Volta Memorial Workshop on Low-Power Design, 1999, p.52-60

1999

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Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.41-46

2001

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Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.66-70

2001

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A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints

International Symposium on Low Power Electronics and Design: Proceedings of the 1999 international symposium on Low power electronics and design; 16-17 Aug. 1999, 1999, p.270-272

1999

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A multi-PLL clock distribution architecture for gigascale integration

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.30-35

2001

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Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms

Proceedings of the IEEE, 1990-02, Vol.78 (2), p.319-335

1990

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Calculation of the emitter efficiency of bipolar transistors

IEEE transactions on electron devices, 1973-09, Vol.20 (9), p.772-778

1973

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Differences in nonspecific bronchial responsiveness between patients with asthma and patients with rhinitis are not explained by type and degree of inhalant allergy

International archives of allergy and immunology, 1997-01, Vol.112 (1), p.65-72

1997

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LUT-based FPGA technology mapping for power minimization with optimal depth

Proceedings IEEE Computer Society Workshop on VLSI 2001. Emerging Technologies for VLSI Systems, 2001, p.123-128

2001

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Seasonal prediction of Horn of Africa long rains using machine learning: The pitfalls of preselecting correlated predictors

Dosing of piperacillin/tazobactam in a morbidly obese patient

Comparison of Allergen-Induced Late Inflammatory Reactions in the Nose and in the Skin in House Dust Mite-Allergic Patients with or without Asthma

A systematic methodology for the application of data transfer and storage optimizing code transformations for power consumption and execution time reduction in realizations of multimedia algorithms on programmable processors

Evolution of substrate noise generation mechanisms with CMOS technology scaling

Beyond the horizon: The next 10x reduction in power - Challenges and solutions

Clock-skew-optimization methodology for substrate-noise reduction with supply-current folding

A linear threshold gate implementation in single electron technology

Energy-efficient link layer for wireless microsensor networks

Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors

Transport equations in heavy doped silicon

A 1-GSPS CMOS flash A/D converter for system-on-chip applications

SITCAP -- A simulator of bipolar transistors for computer-aided circuit analysis programs

A performance-oriented use methodology of power optimizing code transformations for multimedia applications realized on programmable multimedia processors

Background memory area estimation for multidimensional signal processing systems

A novel architecture for low-power design of parallel multipliers

Interaction between sub-word parallelism exploitation and low power code transformations for VLIW multi-media processors

Design and implementation of a coarse-grained dynamically reconfigurable hardware architecture

Current sensing techniques for global interconnects in very deep submicron (VDSM) CMOS

A methodology for power efficient partitioning of data-dominated algorithm specifications within performance constraints

A multi-PLL clock distribution architecture for gigascale integration

Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms

Calculation of the emitter efficiency of bipolar transistors

Differences in nonspecific bronchial responsiveness between patients with asthma and patients with rhinitis are not explained by type and degree of inhalant allergy

LUT-based FPGA technology mapping for power minimization with optimal depth

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