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A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks

IEEE transactions on circuits and systems. I, Regular papers, 2024-04, Vol.71 (4), p.1602-1614

2024

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A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

IEEE access, 2024, Vol.12, p.48555-48569

2024

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ORSAS: An Output Row-Stationary Accelerator for Sparse Neural Networks

IEEE access, 2023-01, Vol.11, p.1-1

2023

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A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications

2024 IEEE International Symposium on Circuits and Systems (ISCAS), 2024, p.1-5

2024

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Gradient Corrected Approximation for Binary Neural Networks

IEICE Transactions on Information and Systems, 2021/10/01, Vol.E104.D(10), pp.1784-1788

2021

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A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

Electronics (Basel), 2022-09, Vol.11 (17), p.2685

2022

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High-Speed Object Recognition Based on a Neuromorphic System

Electronics (Basel), 2022-12, Vol.11 (24), p.4179

2022

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Increasing Information Entropy of Both Weights and Activations for the Binary Neural Networks

Electronics (Basel), 2021-08, Vol.10 (16), p.1943

2021

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HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method

IEEE access, 2023, Vol.11, p.119711-119721

2023

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Regularized Spectral Spike Response Model: A Neuron Model for Robust Parameter Reduction

Brain sciences, 2022-07, Vol.12 (8), p.1008

2022

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Blended Glial Cell's Spiking Neural Network

IEEE access, 2023, Vol.11, p.43566-43582

2023

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An exponential function accelerator with radix-16 algorithm for spiking neural networks

IEICE Electronics Express, 2023-04, Vol.20 (8), p.20220393-20220393, Article 19.20220393

2023

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Concurrent Multiresource Arbiter: Design and Applications

IEEE transactions on computers, 2013-01, Vol.62 (1), p.31-44

2013

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Design of low latency asynchronous arbiter based on standard cell library

IEICE Electronics Express, 2022-10, Vol.19 (19), p.20220265-20220265, Article 19.20220265

2022

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Wide-range, reference free, on-chip voltage sensor for variable Vdd operations

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.37-40

2013

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Differentiable architecture search with multi-dimensional attention for spiking neural networks

Neurocomputing (Amsterdam), 2024-10, Vol.601, p.128181, Article 128181

2024

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SRRT: An Ultra-Low Power Unidirectional Single-Wire Inter-Chip Communication for IoT

IEEE transactions on circuits and systems. II, Express briefs, 2024-10, p.1-1

2024

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Phase-Encoding for On-Chip Signalling

IEEE transactions on circuits and systems. I, Regular papers, 2008-03, Vol.55 (2), p.535-545

2008

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Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments

IEEE journal on emerging and selected topics in circuits and systems, 2013-03, Vol.3 (1), p.35-44

2013

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Function-selectable Bitwise Operation Accelerators

2023 8th International Conference on Integrated Circuits and Microsystems (ICICM), 2023, p.488-492

2023

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A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011, p.89-98

2011

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Variation Tolerant AFPGA Architecture

2011 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011, p.77-86

2011

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Asynchronous FPGA architecture with distributed control

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.1436-1439

2010

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Highly parallel multi-resource arbiters

2010 IEEE International Symposium on Circuits and Systems (ISCAS), 2010, p.4117-4120

2010

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Modular Approach to Multi-resource Arbiter Design

2009 15th IEEE Symposium on Asynchronous Circuits and Systems, 2009, p.107-116

2009

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A 1-8b Reconfigurable Digital SRAM Compute-in-Memory Macro for Processing Neural Networks

A Lightweight and High-Throughput Asynchronous Message Bus for Communication in Multi-Core Heterogeneous Systems

ORSAS: An Output Row-Stationary Accelerator for Sparse Neural Networks

A 409mV, Sub-10nW Power-on Reset Circuit Using Adaptive Accuracy Adjustment for Low Voltage Applications

Gradient Corrected Approximation for Binary Neural Networks

A Low-Power Area-Efficient Precision Scalable Multiplier with an Input Vector Systolic Structure

High-Speed Object Recognition Based on a Neuromorphic System

Increasing Information Entropy of Both Weights and Activations for the Binary Neural Networks

HPSAP: A High-Performance and Synthesizable Asynchronous Pipeline With Quasi-2phase Conversion Method

Regularized Spectral Spike Response Model: A Neuron Model for Robust Parameter Reduction

Blended Glial Cell's Spiking Neural Network

An exponential function accelerator with radix-16 algorithm for spiking neural networks

Concurrent Multiresource Arbiter: Design and Applications

Design of low latency asynchronous arbiter based on standard cell library

Wide-range, reference free, on-chip voltage sensor for variable Vdd operations

Differentiable architecture search with multi-dimensional attention for spiking neural networks

SRRT: An Ultra-Low Power Unidirectional Single-Wire Inter-Chip Communication for IoT

Phase-Encoding for On-Chip Signalling

Voltage Sensing Using an Asynchronous Charge-to-Digital Converter for Energy-Autonomous Environments

Function-selectable Bitwise Operation Accelerators

A Novel Power Delivery Method for Asynchronous Loads in Energy Harvesting Systems

Variation Tolerant AFPGA Architecture

Asynchronous FPGA architecture with distributed control

Highly parallel multi-resource arbiters

Modular Approach to Multi-resource Arbiter Design

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