UB Paderborn / Katalog / Suche / in CDI

Sortiert nach

Einfacher Volltextzugriff von (fast) überall

Installieren Sie die LibKey Nomad-Browsererweiterung und erhalten Sie von vielen Webseiten einfachen Zugriff auf lizenzierte Volltexte oder Open Access Publikationen. Mehr erfahren...

Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

IEEE journal of solid-state circuits, 2018-07, Vol.53 (7), p.2101-2113

2018

Volltextzugriff (PDF)

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

IEEE transactions on electron devices, 2010-01, Vol.57 (1), p.256-262

2010

Volltextzugriff (PDF)

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

1st ed. 2019., 2019

Volltextzugriff (PDF)

An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil

IEEE journal of solid-state circuits, 2012-01, Vol.47 (1), p.284-291

2012

Volltextzugriff (PDF)

A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

IEEE journal of solid-state circuits, 2020-06, Vol.55 (6), p.1577-1587

2020

Volltextzugriff (PDF)

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

IEEE electron device letters, 2010-06, Vol.31 (6), p.549-551

2010

Volltextzugriff (PDF)

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

IEEE journal of solid-state circuits, 2022-02, Vol.57 (2), p.651-660

2022

Volltextzugriff (PDF)

An all LTPS-TFT based Charge-Integrating-Amplifier for Sensor-Array Readout Circuit on Flexible Substrate

IEEE open journal of solid-state circuits, 2022, Vol.2, p.1-1

2022

Volltextzugriff (PDF)

Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes

Scientific reports, 2017-07, Vol.7 (1), p.5016-7, Article 5016

2017

Volltextzugriff (PDF)

Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors

Applied physics letters, 2016-01, Vol.108 (2)

2016

Volltextzugriff (PDF)

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

IEEE transactions on circuits and systems. I, Regular papers, 2024-01, Vol.71 (1), p.1-7

2024

Volltextzugriff (PDF)

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link

IEEE journal of solid-state circuits, 2012-07, Vol.47 (7), p.1784-1796

2012

Volltextzugriff (PDF)

Highly efficient entropy extraction for true random number generators on FPGAs

2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, p.1-6

2015

Volltextzugriff (PDF)

9th Grade Students' Understanding and Strategies When Solving x(t) Problems in 1D Kinematics and y(x) Problems in Mathematics

Physical review. Physics education research, 2019-01, Vol.15 (1), p.010101, Article 010101

2019

Volltextzugriff (PDF)

A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs

IEEE journal of solid-state circuits, 2017-07, Vol.52 (7), p.1904-1914

2017

Volltextzugriff (PDF)

Crossover Logic: A Low-Power Topology for Unipolar Dual-Gate Thin-Film Technologies

IEEE solid-state circuits letters, 2019-07, Vol.2 (7), p.49-52

2019

Volltextzugriff (PDF)

Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for $< $100 nA Error

IEEE transactions on biomedical circuits and systems, 2023-10, Vol.17 (5), p.1166-1176

2023

Volltextzugriff (PDF)

Complementary integrated circuits on plastic foil using inkjet printed n- and p-type organic semiconductors: Fabrication, characterization, and circuit analysis

Organic electronics, 2012-09, Vol.13 (9), p.1686-1692

2012

Volltextzugriff (PDF)

Dense, 11 V-tolerant, Balanced Stimulator IC with Digital Time-domain Calibration for <100nA Error

IEEE transactions on biomedical circuits and systems, 2023-06, Vol.PP, p.1-11

2023

Volltextzugriff (PDF)

Design and Validation of a Test for Representational Fluency of 9th Grade Students in Physics and Mathematics: The Case of Linear Functions

Physical review. Physics education research, 2018-08, Vol.14 (2), p.020105, Article 020105

2018

Volltextzugriff (PDF)

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

Semiconductor science and technology, 2011-08, Vol.26 (8), p.085001

2011

Volltextzugriff (PDF)

Toward a Framework of Integrating Ability: Conceptualization and Design of an Integrated Physics and Mathematics Test

Education sciences, 2023-03, Vol.13 (3), p.249

2023

Volltextzugriff (PDF)

A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications

IEEE journal of solid-state circuits, 2024-08, p.1-12

2024

Volltextzugriff (PDF)

An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture

IEEE journal of solid-state circuits, 2024-02, Vol.59 (2), p.1-12

2024

Volltextzugriff (PDF)

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

Journal of the Society for Information Display, 2017-04, Vol.25 (4), p.222-228

2017

Volltextzugriff (PDF)

1 – 25 von 335

Suche als RSS-Feed

Suchergebnisse filtern

Filter anzeigen

Nur zeigen

Geprüft (Peer-Review)
(151)
Mit Volltextzugriff
(290)

Publikationsform

1 weiteren anzeigen...

Weniger anzeigen...

Sprache

Erscheinungsjahr

n.n

Thema

Science & Technology
(204)
Technology
(202)
Engineering
(193)
Engineering, Electrical & Electronic
(188)
Computer Science
(55)
Energy Consumption
(50)
Transistors
(49)
Computer Science, Hardware & Architecture
(44)
Integrated Circuits
(44)
Applied Sciences
(42)
Exact Sciences And Technology
(42)
Physics
(41)
Electronics
(40)
Physical Sciences
(40)
Random Access Memory
(37)
Logic Gates
(35)
Physics, Applied
(34)
Semiconductor Electronics. Microelectronics. Optoelectronics. Solid State Devices
(34)
Circuits
(31)
Voltage
(31)

15 weitere anzeigen...

Weniger anzeigen...

Neu hinzugefügt

... seit 90 Tagen
(3)

Menü

Weitere Dienste

Einstellungen

Margin Elimination Through Timing Error Detection in a Near-Threshold Enabled 32-bit Microcontroller in 40-nm CMOS

Electrical Modeling and Characterization of Through Silicon via for Three-Dimensional ICs

Efficient Design of Variation-Resilient Ultra-Low Energy Digital Processors

An 8-Bit, 40-Instructions-Per-Second Organic Microprocessor on Plastic Foil

A 5-GS/s 7.2-ENOB Time-Interleaved VCO-Based ADC Achieving 30.5 fJ/cs

Through-Silicon-Via Capacitance Reduction Technique to Benefit 3-D IC Performance

Design Margin Reduction Through Completion Detection in a 28-nm Near-Threshold DSP Processor

An all LTPS-TFT based Charge-Integrating-Amplifier for Sensor-Array Readout Circuit on Flexible Substrate

Material-Device-Circuit Co-optimization of 2D Material based FETs for Ultra-Scaled Technology Nodes

Comparison of short-channel effects in monolayer MoS2 based junctionless and inversion-mode field-effect transistors

A 1MHz 256kb Ultra Low Power Memory Macro for Biomedical Recording Applications in 22nm FD-SOI Using FECC to Enable Data Retention Down to 170mV Supply Voltage

A 65 nm, 850 MHz, 256 kbit, 4.3 pJ/access, Ultra Low Leakage Power Memory Using Dynamic Cell Stability and a Dual Swing Data Link

Highly efficient entropy extraction for true random number generators on FPGAs

9th Grade Students' Understanding and Strategies When Solving x(t) Problems in 1D Kinematics and y(x) Problems in Mathematics

A Differential Transmission Gate Design Flow for Minimum Energy Sub-10-pJ/Cycle ARM Cortex-M0 MCUs

Crossover Logic: A Low-Power Topology for Unipolar Dual-Gate Thin-Film Technologies

Dense, 11 V-Tolerant, Balanced Stimulator IC with Digital Time-Domain Calibration for $< $100 nA Error

Complementary integrated circuits on plastic foil using inkjet printed n- and p-type organic semiconductors: Fabrication, characterization, and circuit analysis

Dense, 11 V-tolerant, Balanced Stimulator IC with Digital Time-domain Calibration for <100nA Error

Design and Validation of a Test for Representational Fluency of 9th Grade Students in Physics and Mathematics: The Case of Linear Functions

Digital-circuit analysis of short-gate tunnel FETs for low-voltage applications

Toward a Framework of Integrating Ability: Conceptualization and Design of an Integrated Physics and Mathematics Test

A 12-nm High-Density Energy-Efficient 1-Mb 2R2W Scratchpad With Local Blocks for Neural Network Applications

An Ultrasonic Driver Array in Metal-Oxide Thin-Film Technology Using a Hybrid TFT-Si DLL Locking Architecture

Power saving through state retention in IGZO‐TFT AMOLED displays for wearable applications

Suchergebnisse filtern