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Impact of polysilicon emitter interfacial layer engineering on the 1/f noise of bipolar transistors

IEEE transactions on electron devices, 1996-12, Vol.43 (12), p.2261-2268

1996

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Modeling the subthreshold swing in MOSFET's

IEEE electron device letters, 1997-08, Vol.18 (8), p.369-371

1997

Volltextzugriff (PDF)

Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model

Solid-state electronics, 2002-03, Vol.46 (3), p.353-360

2002

Volltextzugriff (PDF)

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOS technologies

IEEE transactions on electron devices, 2000-11, Vol.47 (11), p.2153-2160

2000

Volltextzugriff (PDF)

Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications

IEEE transactions on electron devices, 1992-05, Vol.39 (5), p.1150-1156

1992

Volltextzugriff (PDF)

A global description of the base current 1/ f noise of polysilicon emitter bipolar transistors before and after hot-carrier stress

Solid-state electronics, 1998-09, Vol.42 (9), p.1679-1687

1998

Volltextzugriff (PDF)

Substrate bonding techniques for CMOS processed wafers

Journal of micromechanics and microengineering, 1997-09, Vol.7 (3), p.108-110

1997

Volltextzugriff (PDF)

A new method for measuring the saturation velocity of submicron CMOS transistors

Solid-state electronics, 1995-04, Vol.38 (4), p.791-793

1995

Volltextzugriff (PDF)

Impact of the transmission line properties of a metal-ultrathin silicon dioxide-semiconductor field-effect transistor on the extracted inversion-layer thickness

Journal of applied physics, 1998-02, Vol.83 (4), p.2131-2138

1998

Volltextzugriff (PDF)

CMOS options for single chip applications

IEEE MICRO, 1999-09, Vol.19 (5), p.23-32

1999

Volltextzugriff (PDF)

Comprehensive closed-form model for the quantized accumulation layer in MOS structures

Solid-state electronics, 1998-01, Vol.42 (1), p.49-56

1998

Volltextzugriff (PDF)

The behavior of silicon p-n junction-based devices at liquid helium temperatures

Journal of applied physics, 1991-07, Vol.70 (2), p.1016-1024

1991

Volltextzugriff (PDF)

Investigation of the high frequency noise figure reduction of SiGe heterojunction bipolar transistors using actualised physical models

Solid-state electronics, 1995, Vol.38 (1), p.157-162

1995

Volltextzugriff (PDF)

Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

IEEE transactions on electron devices, 1996-09, Vol.43 (9), p.1407-1415

1996

Volltextzugriff (PDF)

The charge transport in a silicon resistor at liquid-helium temperatures

Journal of applied physics, 1990-10, Vol.68 (8), p.4091-4099

1990

Volltextzugriff (PDF)

The importance of the internal bulk-source potential on the low temperature kink in NMOSTs

IEEE transactions on electron devices, 1991-06, Vol.38 (6), p.1459-1466

1991

Volltextzugriff (PDF)

Small geometry effects on the maximum cutoff frequency of bipolar transistors

ESSDERC '92: 22nd European Solid State Device Research conference, 1992, Vol.19 (1), p.707-710

1992

Volltextzugriff (PDF)

On the optimisation of outside spacer bipolar transistors for 0.5 μm high performance mixed analog/digital BiCMOS

Electrical engineering, 1996-10, Vol.79 (5), p.343-351

1996

Volltextzugriff (PDF)

Experimental determination of self-heating in submicrometer MOS transistors operated in a liquid-helium ambient

IEEE electron device letters, 1993-03, Vol.14 (3), p.152-154

1993

Volltextzugriff (PDF)

HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications

IEEE transactions on electron devices, 1993-12, Vol.40 (12), p.2255-2263

1993

Volltextzugriff (PDF)

DC characteristics of submicrometer CMOS inverters operating over the whole temperature range of 4.2-300 K

IEEE transactions on electron devices, 1992-09, Vol.39 (9), p.2182-2184

1992

Volltextzugriff (PDF)

Carrier multiplication in submicrometre pMOS transistors operated at cryogenic temperatures

Electronics letters, 1992, Vol.28 (3), p.229-231

1992

Volltextzugriff (PDF)

Polyoxide edge tunneling current reduction by top corner rounding

Microelectronic engineering, 1992, Vol.19 (1), p.721-724

1992

Volltextzugriff (PDF)

Integration challenges in sub-0.25 μm CMOS-based technologies

Microelectronics, 2000-12, Vol.31 (11-12), p.861-871

2000

Volltextzugriff (PDF)

Study of the hot-carrier degradation performance of 0.35-μm fully overlapped LDD devices

Microelectronic engineering, 1995-06, Vol.28 (1), p.265-268

1995

Volltextzugriff (PDF)

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Impact of polysilicon emitter interfacial layer engineering on the 1/f noise of bipolar transistors

Modeling the subthreshold swing in MOSFET's

Development of a RF large signal MOSFET model, based on an equivalent circuit, and comparison with the BSIM3v3 compact model

Embedded HIMOS(R) flash memory in 0.35 μm and 0.25 μm CMOS technologies

Analysis of the enhanced hot-electron injection in split-gate transistors useful for EEPROM applications

A global description of the base current 1/ f noise of polysilicon emitter bipolar transistors before and after hot-carrier stress

Substrate bonding techniques for CMOS processed wafers

A new method for measuring the saturation velocity of submicron CMOS transistors

Impact of the transmission line properties of a metal-ultrathin silicon dioxide-semiconductor field-effect transistor on the extracted inversion-layer thickness

CMOS options for single chip applications

Comprehensive closed-form model for the quantized accumulation layer in MOS structures

The behavior of silicon p-n junction-based devices at liquid helium temperatures

Investigation of the high frequency noise figure reduction of SiGe heterojunction bipolar transistors using actualised physical models

Performance and reliability aspects of FOND: a new deep submicron CMOS device concept

The charge transport in a silicon resistor at liquid-helium temperatures

The importance of the internal bulk-source potential on the low temperature kink in NMOSTs

Small geometry effects on the maximum cutoff frequency of bipolar transistors

On the optimisation of outside spacer bipolar transistors for 0.5 μm high performance mixed analog/digital BiCMOS

Experimental determination of self-heating in submicrometer MOS transistors operated in a liquid-helium ambient

HIM0S-a high efficiency flash E/sup 2/PROM cell for embedded memory applications

DC characteristics of submicrometer CMOS inverters operating over the whole temperature range of 4.2-300 K

Carrier multiplication in submicrometre pMOS transistors operated at cryogenic temperatures

Polyoxide edge tunneling current reduction by top corner rounding

Integration challenges in sub-0.25 μm CMOS-based technologies

Study of the hot-carrier degradation performance of 0.35-μm fully overlapped LDD devices

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