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RIE dynamics for extreme wafer thinning applications

Microelectronic engineering, 2018-05, Vol.192, p.30-37

2018

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The Increasing Role of Polymers in Advanced Packaging - From Stress Buffer Layers to Wafer Level Underfills and Beyond

Journal of Photopolymer Science and Technology, 2017/06/26, Vol.30(1), pp.17-24

2017

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Influence of Si wafer thinning processes on (sub)surface defects

Applied surface science, 2017-05, Vol.404, p.82-87

2017

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Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

Japanese Journal of Applied Physics, 2015-05, Vol.54 (5S), p.5

2015

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A study on substrate noise coupling among TSVs in 3D chip stack

IEICE Electronics Express, 2018, Vol.15 (13), p.20180460-20180460

2018

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Wafer-to-wafer hybrid bonding at 400-nm interconnect pitch

Nature Reviews Electrical Engineering, 2024-02, Vol.1 (2), p.71-72

2024

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Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.2095-2102

2016

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Investigation of Distortion in Wafer-to-wafer Bonding with Highly Bowed Wafers

2024 IEEE 74th Electronic Components and Technology Conference (ECTC), 2024, p.386-393

2024

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Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.42-48

2020

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Manufacturability of microLED on CMOS for Augmented Reality Glasses

Proceedings of the International Display Workshops, 2023-12, p.176

2023

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4‐3: MircoLED display on 300mm CMOS platform – crosstalk and optical outcoupling

SID International Symposium Digest of technical papers, 2023-06, Vol.54 (1), p.25-28

2023

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Anomalous – Inversion in TSVs: The Problem and Its Cure

IEEE transactions on electron devices, 2018-04, Vol.65 (4), p.1473-1479

2018

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A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage

2023 IEEE 73rd Electronic Components and Technology Conference (ECTC), 2023, p.1410-1417

2023

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Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

Journal of electronic packaging, 2016-03, Vol.138 (1)

2016

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Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding

2021 IEEE 71st Electronic Components and Technology Conference (ECTC), 2021, p.2097-2104

2021

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57‐3: MircoLED Display Integration on 300mm Advanced CMOS Platform

SID International Symposium Digest of technical papers, 2022-06, Vol.53 (1), p.748-751

2022

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Etch process modules development and integration in 3D-SOC applications

Microelectronic engineering, 2018-09, Vol.196, p.38-48

2018

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Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

IEEE transactions on components, packaging, and manufacturing technology (2011), 2020-09, Vol.10 (9), p.1542-1551

2020

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3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenomena in Electronic Systems (ITherm), 2020, p.219-228

2020

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Impact of Via Density on the Mechanical Integrity of Advanced Back-End-of-Line During Packaging

2016 IEEE 66th Electronic Components and Technology Conference (ECTC), 2016, p.1778-1785

2016

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Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects

Microelectronics and reliability, 2017-12, Vol.79, p.297-305

2017

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Advanced experimental back-end-of-line (BEOL) stability test: Measurements and simulations

Microelectronic engineering, 2015-04, Vol.137, p.54-58

2015

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High-k Materials for Tunnel Barrier Engineering in Floating-Gate Flash Memories

ECS transactions, 2006-07, Vol.1 (5), p.75-89

2006

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First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency

IEEE transactions on electron devices, 2012-10, Vol.59 (10), p.2723-2726

2012

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Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

2020 IEEE 70th Electronic Components and Technology Conference (ECTC), 2020, p.216-222

2020

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RIE dynamics for extreme wafer thinning applications

The Increasing Role of Polymers in Advanced Packaging - From Stress Buffer Layers to Wafer Level Underfills and Beyond

Influence of Si wafer thinning processes on (sub)surface defects

Effect of test structure on electromigration characteristics in three-dimensional through silicon via stacked devices

A study on substrate noise coupling among TSVs in 3D chip stack

Wafer-to-wafer hybrid bonding at 400-nm interconnect pitch

Characterization of Extreme Si Thinning Process for Wafer-to-Wafer Stacking

Investigation of Distortion in Wafer-to-wafer Bonding with Highly Bowed Wafers

Extreme Wafer Thinning and nano-TSV processing for 3D Heterogeneous Integration

Manufacturability of microLED on CMOS for Augmented Reality Glasses

4‐3: MircoLED display on 300mm CMOS platform – crosstalk and optical outcoupling

Anomalous – Inversion in TSVs: The Problem and Its Cure

A Study of SiCN Wafer-to-Wafer Bonding and Impact of Wafer Warpage

Experimental Characterization of the Vertical and Lateral Heat Transfer in Three-Dimensional Stacked Die Packages

Characterization of bonding activation sequences to enable ultra-low Cu/SiCN wafer level hybrid bonding

57‐3: MircoLED Display Integration on 300mm Advanced CMOS Platform

Etch process modules development and integration in 3D-SOC applications

Optical Beam-Based Defect Localization Methodologies for Open and Short Failures in Micrometer-Scale 3-D TSV Interconnects

3D Wafer-to-Wafer Bonding Thermal Resistance Comparison: Hybrid Cu/dielectric Bonding versus Dielectric via-last Bonding

Impact of Via Density on the Mechanical Integrity of Advanced Back-End-of-Line During Packaging

Impact of via density and passivation thickness on the mechanical integrity of advanced Back-End-Of-Line interconnects

Advanced experimental back-end-of-line (BEOL) stability test: Measurements and simulations

High-k Materials for Tunnel Barrier Engineering in Floating-Gate Flash Memories

First Demonstration of Hybrid CMOS Imagers With Simultaneous Very Low Crosstalk and High-Broadband Quantum Efficiency

Novel Cu/SiCN surface topography control for 1 μm pitch hybrid wafer-to-wafer bonding

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