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On System-on-Chip Testing Using Hybrid Test Vector Compression

IEEE transactions on instrumentation and measurement, 2014-11, Vol.63 (11), p.2611-2619

2014

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Face Identification Based on Discrete Wavelet Transform and Neural Networks

International journal of image and graphics, 2019-10, Vol.19 (4), p.1950022

2019

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Low-level logic fault testing ASIC simulation environment

World journal of engineering, 2014-06, Vol.11 (3), p.279-286

2014

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Energy efficient optimization of wireless embedded sensor networks

World journal of engineering, 2013-09, Vol.10 (3), p.273-282

2013

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Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-05, Vol.37 (5), p.1037-1049

2018

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Response compression in space with cascade of two-input linear and nonlinear logic

World journal of engineering, 2013-09, Vol.10 (3), p.283-296

2013

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On automated test system for asymmetric digital subscriber line equipment

World journal of engineering, 2013-01, Vol.10 (4), p.387-394

2013

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Cascade of two-input nonlinear logic in designing space compression networks in VLSI

World journal of engineering, 2012-06, Vol.9 (3), p.199-206

2012

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Epileptic Seizure Detection Using Convolution Neural Networks

2022 IEEE International Symposium on Medical Measurements and Applications (MeMeA), 2022, p.1-5

2022

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Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status

World journal of engineering, 2013-03, Vol.10 (1), p.73-84

2013

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Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

World journal of engineering, 2012-01, Vol.9 (6), p.519-528

2012

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An Optimized Tongue Drive System for Disabled Persons

2021 IEEE International Instrumentation and Measurement Technology Conference (I2MTC), 2021, p.1-6

2021

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Real Time Intelligent Traffic Light System

WSEAS TRANSACTIONS ON SYSTEMS, 2020-02, Vol.19, p.20-25

2020

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Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment

Intelligent Information Technology, 2004, p.315-325

2004

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An adaptive compressed MPEG-2 video watermarking scheme

IEEE transactions on instrumentation and measurement, 2005-10, Vol.54 (5), p.1853-1861

2005

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Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm

2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2016, p.1-6

2016

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PGEN: A Novel Approach to Sequential Circuit Test Generation

VLSI Design, 1996-01, Vol.1996 (3), p.149-165

1996

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A compact multispectral image capture unit for deployment on drones

2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2016, p.1-5

2016

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Designing Home Security and Monitoring System Based on Field Programmable Gate Array

Technical review - IETE, 2014-03, Vol.31 (2), p.168-176

2014

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An algorithm for generating prime implicants

2016 IEEE International Instrumentation and Measurement Technology Conference Proceedings, 2016, p.1-6

2016

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Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach

IEEE transactions on instrumentation and measurement, 2007-06, Vol.56 (3), p.840-855

2007

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Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

Distributed Computing, 2002, p.234-245

2002

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Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

IEEE transactions on instrumentation and measurement, 2005-06, Vol.54 (3), p.941-955

Das, S.R.

2005

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Molecular Pathology in Cancer Research

1st ed. 2016 edition., 2017

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Space compactor design in VLSI circuits based on graph theoretic concepts

IEEE transactions on instrumentation and measurement, 2006-08, Vol.55 (4), p.1106-1118

2006

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On System-on-Chip Testing Using Hybrid Test Vector Compression

Face Identification Based on Discrete Wavelet Transform and Neural Networks

Low-level logic fault testing ASIC simulation environment

Energy efficient optimization of wireless embedded sensor networks

Memristor-Based High-Speed Memory Cell With Stable Successive Read Operation

Response compression in space with cascade of two-input linear and nonlinear logic

On automated test system for asymmetric digital subscriber line equipment

Cascade of two-input nonlinear logic in designing space compression networks in VLSI

Epileptic Seizure Detection Using Convolution Neural Networks

Fault-tolerance in VLSI systems design using data compression under constraints of failure probabilities-overview and current status

Implementing built-in self-test environment for cores-based digital circuits with Verilog HDL

An Optimized Tongue Drive System for Disabled Persons

Real Time Intelligent Traffic Light System

Implementation of Embedded Cores-Based Digital Devices in JBits Java Simulation Environment

An adaptive compressed MPEG-2 video watermarking scheme

Short duration voice data speaker recognition system using novel fuzzy vector quantization algorithm

PGEN: A Novel Approach to Sequential Circuit Test Generation

A compact multispectral image capture unit for deployment on drones

Designing Home Security and Monitoring System Based on Field Programmable Gate Array

An algorithm for generating prime implicants

Testing Analog and Mixed-Signal Circuits With Built-In Hardware-A New Approach

Design of Aliasing Free Space Compressor in BIST with Maximal Compaction Ratio Using Concepts of Strong and Weak Compatibilities of Response Data Outputs and Generalized Sequence Mergeability

Getting errors to catch themselves - self-testing of VLSI circuits with built-in hardware

Molecular Pathology in Cancer Research

Space compactor design in VLSI circuits based on graph theoretic concepts

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