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Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications

IEEE transactions on circuits and systems for video technology, 2015-03, Vol.25 (3), p.497-507

2015

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A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

IEEE transactions on multimedia, 2014-12, Vol.16 (8), p.2323-2332

2014

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High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

IEEE transactions on very large scale integration (VLSI) systems, 2015-12, Vol.23 (12), p.3138-3142

2015

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VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications

IEEE transactions on circuits and systems for video technology, 2017-02, Vol.27 (2), p.380-393

2017

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Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

IEEE transactions on multimedia, 2017-11, Vol.19 (11), p.2375-2390

2017

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A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder

IEEE journal of solid-state circuits, 2014-04, Vol.49 (4), p.827-837

2014

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Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1032-1037

2017

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An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

IEEE journal of solid-state circuits, 2017-01, Vol.52 (1), p.113-126

2017

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A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

IEEE transactions on very large scale integration (VLSI) systems, 2017-02, Vol.25 (2), p.714-724

2017

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A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

IEEE journal of solid-state circuits, 2011-04, Vol.46 (4), p.777-788

2011

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Lossy Compression for Embedded Computer Vision Systems

IEEE access, 2018-01, Vol.6, p.39385-39397

2018

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Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing

IEICE transactions on electronics, 2018-04, Vol.E101.C (4), p.263-272

2018

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An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding

IEEE transactions on multimedia, 2012-04, Vol.14 (2), p.237-249

2012

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A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications

IEEE transactions on very large scale integration (VLSI) systems, 2015-12, Vol.23 (12), p.2768-2781

2015

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Accelerating HEVC Inter Prediction with Improved Merge Mode Handling

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-02, Vol.E100.A (2), p.546-554

2017

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Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (12), p.2869-2877

2017

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Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction

MultiMedia Modeling, p.541-552

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Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2017-01, Vol.E100.A (11), p.2416-2424

2017

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Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC

Journal of visual communication and image representation, 2014-07, Vol.25 (5), p.1275-1286

2014

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Embedded Frame Compression for Energy-Efficient Computer Vision Systems

2018 IEEE International Symposium on Circuits and Systems (ISCAS), 2018, p.1-5

2018

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A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2013, Vol.E96.A (12), p.2612-2622

2013

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A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor

IEICE transactions on electronics, 2017-01, Vol.E100.C (3), p.223-231

2017

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A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform

IEICE transactions on fundamentals of electronics, communications and computer sciences, 2016, Vol.E99.A (12), p.2375-2387

2016

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OpenCL based high-quality HEVC motion estimation on GPU

2014 IEEE International Conference on Image Processing (ICIP), 2014, p.1263-1267

2014

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High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications

IEEE transactions on very large scale integration (VLSI) systems, 2014-01, Vol.22 (1), p.76-89

2014

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Ultra-High-Throughput VLSI Architecture of H.265/HEVC CABAC Encoder for UHDTV Applications

A New Reference Frame Recompression Algorithm and Its VLSI Architecture for UHDTV Video Codec

High-Throughput Power-Efficient VLSI Architecture of Fractional Motion Estimation for Ultra-HD HEVC Video Encoding

VLSI Implementation of HEVC Motion Compensation With Distance Biased Direct Cache Mapping for 8K UHDTV Applications

Fast Algorithm and VLSI Architecture of Rate Distortion Optimization in H.265/HEVC

A 1.59 Gpixel/s Motion Estimation Processor With -211 to +211 Search Range for UHDTV Video Encoder

Chain-NN: An energy-efficient 1D chain architecture for accelerating deep convolutional neural networks

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

A Dual-Clock VLSI Design of H.265 Sample Adaptive Offset Estimation for 8k Ultra-HD TV Encoding

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Lossy Compression for Embedded Computer Vision Systems

Approximate-DCT-Derived Measurement Matrices with Row-Operation-Based Measurement Compression and its VLSI Architecture for Compressed Sensing

An Advanced Hierarchical Motion Estimation Scheme With Lossless Frame Recompression and Early-Level Termination for Beyond High-Definition Video Coding

A Frame-Parallel 2 Gpixel/s Video Decoder Chip for UHDTV and 3-DTV/FTV Applications

Accelerating HEVC Inter Prediction with Improved Merge Mode Handling

Framework and VLSI Architecture of Measurement-Domain Intra Prediction for Compressively Sensed Visual Contents

Low-Complexity Rate-Distortion Optimization Algorithms for HEVC Intra Prediction

Distortion Control and Optimization for Lossy Embedded Compression in Video Codec System

Alternating asymmetric search range assignment for bidirectional motion estimation in H.265/HEVC and H.264/AVC

Embedded Frame Compression for Energy-Efficient Computer Vision Systems

A High Performance HEVC De-Blocking Filter and SAO Architecture for UHDTV Decoder

A 7-Die 3D Stacked 3840×2160@120 fps Motion Estimation Processor

A Low-Power VLSI Architecture for HEVC De-Quantization and Inverse Transform

OpenCL based high-quality HEVC motion estimation on GPU

High-Performance H.264/AVC Intra-Prediction Architecture for Ultra High Definition Video Applications

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