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ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

IEEE transactions on electron devices, 2016-05, Vol.63 (5), p.1996-2002

2016

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Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process

IEEE transactions on electron devices, 2016-06, Vol.63 (6), p.2449-2454

2016

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Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications

IEEE transactions on electron devices, 2018-02, Vol.65 (2), p.798-802

2018

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Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- \mu \text 60-V/5-V BCD Technology

IEEE transactions on electron devices, 2017-08, Vol.64 (8), p.3519-3523

2017

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Study on ESD protection design with stacked low-voltage devices for high-voltage applications

2014 IEEE International Reliability Physics Symposium, 2014, p.EL.5.1-EL.5.2

2014

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Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

2013 IEEE International Conference on Microelectronic Test Structures (ICMTS), 2013, p.127-130

2013

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ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

2015 28th IEEE International System-on-Chip Conference (SOCC), 2015, p.380-383

2015

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Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

2013 International Symposium on Next-Generation Electronics, 2013, p.116-119

2013

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Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

2012 19th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits, 2012, p.1-4

2012

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Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

2018 40th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD), 2018, p.1-6

2018

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ESD Protection Design With Stacked High-Holding-Voltage SCR for High-Voltage Pins in a Battery-Monitoring IC

Optimization of Guard Ring Structures to Improve Latchup Immunity in an 18 V DDDMOS Process

Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications

Investigation of Unexpected Latchup Path Between HV-LDMOS and LV-CMOS in a 0.25- \mu \text 60-V/5-V BCD Technology

Study on ESD protection design with stacked low-voltage devices for high-voltage applications

Investigation on safe operating area and ESD robustness in a 60-V BCD process with different deep P-Well test structures

ESD protection design with stacked low-voltage devices for high-voltage pins of battery-monitoring IC

Self-protected LDMOS output device with embedded SCR to improve ESD robustness in 0.25-μm 60-V BCD process

Failure analysis on gate-driven ESD clamp circuit after TLP stresses of different voltage steps in a 16-V CMOS process

Study on Latchup Path between HV-LDMOS and LV-CMOS in a 0.16-μm 30-V/1.8-V BCD Technology

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