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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

IEEE journal of solid-state circuits, 2018-10, Vol.53 (10), p.2906-2916

2018

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A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

IEEE journal of solid-state circuits, 2024, p.1-9

2024

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A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

IEEE journal of solid-state circuits, 2020-01, Vol.55 (1), p.157-166

2020

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23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019, p.378-380

2019

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22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.382-384

2020

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A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C182-C183

2015

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A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

2022 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2022, p.1-3

2022

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25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014, p.430-431

2014

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A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

2023 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2023, p.1-4

2023

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Highly efficient genome editing by CRISPR-Cpf1 using CRISPR RNA with a uridinylate-rich 3'-overhang

Nature communications, 2018-09, Vol.9 (1), p.3651-11, Article 3651

2018

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Efficient CRISPR editing with a hypercompact Cas12f1 and engineered guide RNAs delivered by adeno-associated virus

Nature biotechnology, 2022-01, Vol.40 (1), p.94-102

2022

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Management Architecture With Multi-modal Ensemble AI Models for Worker Safety

Safety and health at work, 2024-05

2024

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Movement Patterns of Juvenile Loggerhead Turtles ( Caretta caretta L. 1758) and Green Turtles ( Chelonia mydas L. 1758) Hatched in Captivity and Released in the Korean Waters

Animals (Basel), 2022-08, Vol.12 (16), p.2157

2022

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Single-cell RNA sequencing analysis of immune cell population dynamics from peripheral blood in pig-to-non-human primate islet xenotransplantation treated with clinically applicable immunosuppressants

Korean journal of transplantation (Online), 2023-11, Vol.37 (1), p.S259-S259

2023

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Left-Side Surgical Approach to Mitral Valve in Dog Cadaver Study

Journal of veterinary clinics, 2018-02, Vol.35 (1), p.10-12

2018

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Left-Side Surgical Approach to Mitral Valve in Dog Cadaver Study

한국임상수의학회지, 2018, 35(1), , pp.10-12

2018

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Tumor Volume Reduction Assessed by Planning Computed Tomography in Patients with Rectal Cancer during Preoperative Chemoradiation: Impact of Residual Tumor Volume on the Prediction of Pathologic Tumor Regression

Tumori, 2014-03, Vol.100 (2), p.158-162

2014

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Tumor volume reduction assessed by planning computed tomography in patients with rectal cancer during preoperative chemoradiation: impact of residual tumor volume on the prediction of pathologic tumor regression

Tumori, 2014-03, Vol.100 (2), p.158-162

2014

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Iterative decoding of serially concatenated space-time codes in WCDMA systems

MILCOM 2002. Proceedings, 2002, Vol.2, p.911-916 vol.2

2002

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Dual-Loop Two-Step ZQ Calibration for Dynamic Voltage-Frequency Scaling in LPDDR4 SDRAM

A 1.01-V 8.5-Gb/s/pin 16-Gb LPDDR5x SDRAM With Advanced I/O Circuitry for High-Speed and Low-Power Applications

A 7.5 Gb/s/pin 8-Gb LPDDR5 SDRAM With Various High-Speed and Low-Power Techniques

23.1 A 7.5Gb/s/pin LPDDR5 SDRAM With WCK Clocking and Non-Target ODT for High Speed and With DVFS, Internal Data Copy, and Deep-Sleep Mode for Low Power

22.2 An 8.5Gb/s/pin 12Gb-LPDDR5 SDRAM with a Hybrid-Bank Architecture using Skew-Tolerant, Low-Power and Speed-Boosting Techniques in a 2nd generation 10nm DRAM Process

A 6.4Gb/s/pin at sub-1V supply voltage TX-interleaving technique for mobile DRAM interface

A 6-bit 5.12-GS/s Flash ADC with Track-and-Hold Embedded Dynamic Preamplifier in 28nm CMOS

25.1 A 3.2Gb/s/pin 8Gb 1.0V LPDDR4 SDRAM with integrated ECC engine for sub-1V DRAM core operation

A 1.01V 8.5Gb/s/pin 16Gb LPDDR5x SDRAM with Self-Pre-Emphasized Stacked-Tx, Supply Voltage Insensitive Rx, and Optimized Clock Using 4th-Generation 10nm DRAM Process for High-Speed and Low-Power Applications

Highly efficient genome editing by CRISPR-Cpf1 using CRISPR RNA with a uridinylate-rich 3'-overhang

Efficient CRISPR editing with a hypercompact Cas12f1 and engineered guide RNAs delivered by adeno-associated virus

Management Architecture With Multi-modal Ensemble AI Models for Worker Safety

Movement Patterns of Juvenile Loggerhead Turtles ( Caretta caretta L. 1758) and Green Turtles ( Chelonia mydas L. 1758) Hatched in Captivity and Released in the Korean Waters

Single-cell RNA sequencing analysis of immune cell population dynamics from peripheral blood in pig-to-non-human primate islet xenotransplantation treated with clinically applicable immunosuppressants

Left-Side Surgical Approach to Mitral Valve in Dog Cadaver Study

Left-Side Surgical Approach to Mitral Valve in Dog Cadaver Study

Tumor Volume Reduction Assessed by Planning Computed Tomography in Patients with Rectal Cancer during Preoperative Chemoradiation: Impact of Residual Tumor Volume on the Prediction of Pathologic Tumor Regression

Tumor volume reduction assessed by planning computed tomography in patients with rectal cancer during preoperative chemoradiation: impact of residual tumor volume on the prediction of pathologic tumor regression

Iterative decoding of serially concatenated space-time codes in WCDMA systems

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