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Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

IEEE electron device letters, 2015-06, Vol.36 (6), p.600-602

2015

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CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Japanese Journal of Applied Physics, 2018-04, Vol.57 (4S), p.4

2018

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Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

IEEE transactions on electron devices, 2020-12, Vol.67 (12), p.5374-5380

2020

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Dielectric Reliability of 50nm Half Pitch Structures in Aurora® LK

Japanese Journal of Applied Physics, 2009-04

2009

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Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora ® LK HM

Japanese Journal of Applied Physics, 2010-04, Vol.49 (4S), p.4

2010

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Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

IEEE transactions on electron devices, 2020-12, Vol.67 (12), p.5349-5354

2020

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Dielectric Reliability of 50 nm Half Pitch Structures in Aurora ® LK

Japanese Journal of Applied Physics, 2009-04, Vol.48 (4S), p.4

2009

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Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes

Journal of vacuum science & technology. A, Vacuum, surfaces, and films, 2021-07, Vol.39 (4)

2021

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Integration of Porogen-Based Low-$k$ Films: Influence of Capping Layer Thickness and Long Thermal Anneals on Low-$k$ Damage and Reliability

Japanese Journal of Applied Physics, 2010-05, Vol.49 (5), p.05FD03-05FD03-4

2010

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New methodology for modelling MOL TDDB coping with variability

2018 IEEE International Reliability Physics Symposium (IRPS), 2018, p.3A.5-1-3A.5-6

2018

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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO 2 /n-Si Contact

IEEE transactions on electron devices, 2016-07, Vol.63 (7), p.2671-2676

2016

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Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO sub(2)/n-Si Contact

IEEE transactions on electron devices, 2016-07, Vol.63 (7), p.2671-2676

2016

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Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme

2021 IEEE International Integrated Reliability Workshop (IIRW), 2021, p.1-4

2021

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Integration of a templated directed self-assembly-based hole shrink in a short loop via chain

Journal of micro/nanolithography, MEMS, and MOEMS, 2016-10, Vol.15 (4), p.43505

2016

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Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^ Ohm-cm2

IEEE transactions on electron devices, 2016-12, Vol.63 (12), p.4632-4641

2016

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Full reliability study of advanced metallization options for 30 nm A12pitch interconnects

Microelectronic engineering, 2013-06, Vol.106, p.210-213

2013

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(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

ECS transactions, 2017, Vol.77 (5), p.19-30

2017

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Full reliability study of advanced metallization options for 30nm ½pitch interconnects

Microelectronic engineering, 2013-06, Vol.106, p.210-213

2013

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MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

2016 16th International Workshop on Junction Technology (IWJT), 2016, p.19-24

2016

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Reliability of MOL local interconnects

2013 IEEE International Reliability Physics Symposium (IRPS), 2013, p.2F.5.1-2F.5.5

2013

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Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1259-1264

2008

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Direct Copper Electrochemical Deposition on Ru-Based Substrates for Advanced Interconnects Target 30 nm and 1/2 Pitch Lines: From Coupon to Full-Wafer Experiments

ECS transactions, 2011, Vol.35 (2), p.117-123

2011

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Initial void chacterization in 30nm wide polycrystalline Cu line using a local sense EM test structure

2012 IEEE International Reliability Physics Symposium (IRPS), 2012, p.6B.4.1-6B.4.6

2012

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Full reliability study of advanced metallization options for 30 nm ½pitch interconnects

Microelectronic engineering, 2013, Vol.106, p.210-213

2013

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Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

IEEE transactions on electron devices, 2008-05, Vol.55 (5), p.1259-1264

2008

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Multiring Circular Transmission Line Model for Ultralow Contact Resistivity Extraction

CMOS integration of high-k/metal gate transistors in diffusion and gate replacement (D&GR) scheme for dynamic random access memory peripheral circuits

Process Variation Analysis of Device Performance Using Virtual Fabrication: Methodology Demonstrated on a CMOS 14-nm FinFET Vehicle

Dielectric Reliability of 50nm Half Pitch Structures in Aurora® LK

Integration and Dielectric Reliability of 30 nm Half Pitch Structures in Aurora ® LK HM

Buried Power Rail Integration With FinFETs for Ultimate CMOS Scaling

Dielectric Reliability of 50 nm Half Pitch Structures in Aurora ® LK

Engineering high quality and conformal ultrathin SiNx films by PEALD for downscaled and advanced CMOS nodes

Integration of Porogen-Based Low-$k$ Films: Influence of Capping Layer Thickness and Long Thermal Anneals on Low-$k$ Damage and Reliability

New methodology for modelling MOL TDDB coping with variability

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO 2 /n-Si Contact

Thermal Stability Concern of Metal-Insulator-Semiconductor Contact: A Case Study of Ti/TiO sub(2)/n-Si Contact

Channel Length Dependence of PBTI in High-k First RMG Gate Stack Integration Scheme

Integration of a templated directed self-assembly-based hole shrink in a short loop via chain

Titanium Silicide on Si:P With Precontact Amorphization Implantation Treatment: Contact Resistivity Approaching 1 \times 10^ Ohm-cm2

Full reliability study of advanced metallization options for 30 nm A12pitch interconnects

(Invited) Gate-All-Around Transistors Based on Vertically Stacked Si Nanowires

Full reliability study of advanced metallization options for 30nm ½pitch interconnects

MIS or MS? Source/drain contact scheme evaluation for 7nm Si CMOS technology and beyond

Reliability of MOL local interconnects

Manufacturable Processes for < 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

Direct Copper Electrochemical Deposition on Ru-Based Substrates for Advanced Interconnects Target 30 nm and 1/2 Pitch Lines: From Coupon to Full-Wafer Experiments

Initial void chacterization in 30nm wide polycrystalline Cu line using a local sense EM test structure

Full reliability study of advanced metallization options for 30 nm ½pitch interconnects

Manufacturable Processes for \leq 32-nm-node CMOS Enhancement by Synchronous Optimization of Strain-Engineered Channel and External Parasitic Resistances

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