UB Paderborn / Katalog / Suche / in CDI

Faradic Peaks Enhanced by Carbon Nanotubes in Microsomal Cytochrome P450 Electrodes

Electroanalysis (New York, N.Y.), 2015-06, Vol.27 (6), p.1507-1515

2015

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A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis

IEEE transactions on computer-aided design of integrated circuits and systems, 2006-02, Vol.25 (2), p.358-377

2006

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Value-sensitive automatic code specialization for embedded software

IEEE transactions on computer-aided design of integrated circuits and systems, 2002-09, Vol.21 (9), p.1051-1067, Article 1051

2002

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CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.217-222

2019

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Hardware/software co-design

Proceedings of the IEEE, 1997-03, Vol.85 (3), p.349-365

1997

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Supported organic catalysts: synthesis of ( E )-nitrostyrenes from nitroalkanes and aromatic aldehydes over propylamine supported on MCM-41 silica as a reusable catalyst

Tetrahedron letters, 2001-03, Vol.42 (12), p.2401-2403

2001

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A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.172-177

2019

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Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.166-171

2019

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Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.123-128

2019

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The descending branch of lateral femoral circumflex artery in arterial CABG: early and midterm results

The Annals of thoracic surgery, 2003-06, Vol.75 (6), p.1836-1841

2003

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A Hardware-based Framework for Secure Firmware Updates on Embedded Systems

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.198-203

2019

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SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.136-141

2019

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An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.34-39

2019

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Automatic synthesis of low-power gated-clock finite-state machines

IEEE transactions on computer-aided design of integrated circuits and systems, 1996-06, Vol.15 (6), p.630-643

1996

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Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.305-310

2019

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A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.160-165

2019

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Exploiting Approximate Computing to Increase System Lifetime

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.311-316

2019

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Software-Based Self-Test for Transition Faults: a Case Study

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.76-81

2019

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Automated Synthesis of Multi-Port Memories and Control

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.59-64

2019

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Functional Verification of Hardware Dividers using Algebraic Model

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.257-262

2019

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An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.191-196

2019

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Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.88-93

2019

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A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.211-216

2019

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A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.185-190

2019

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Byte-Aware Floating-point Operations through a UNUM Computing Unit

2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration (VLSI-SoC), 2019, p.323-328

2019

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Faradic Peaks Enhanced by Carbon Nanotubes in Microsomal Cytochrome P450 Electrodes

A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis

Value-sensitive automatic code specialization for embedded software

CongestionNet: Routing Congestion Prediction Using Deep Graph Neural Networks

Hardware/software co-design

Supported organic catalysts: synthesis of ( E )-nitrostyrenes from nitroalkanes and aromatic aldehydes over propylamine supported on MCM-41 silica as a reusable catalyst

A Predictive Process Design Kit for Three-Independent-Gate Field-Effect Transistors

Memory Sizing of a Scalable SRAM In-Memory Computing Tile Based Architecture

Non-intrusive Fault Injection Techniques for Efficient Soft Error Vulnerability Analysis

The descending branch of lateral femoral circumflex artery in arterial CABG: early and midterm results

A Hardware-based Framework for Secure Firmware Updates on Embedded Systems

SURF: Self-aware Unified Runtime Framework for Parallel Programs on Heterogeneous Mobile Architectures

An Associativity-Agnostic in-Cache Computing Architecture Optimized for Multiplication

Automatic synthesis of low-power gated-clock finite-state machines

Bottom-Up Approach for High Speed SRAM Word-line Buffer Insertion Optimization

A Product Engine for Energy-Efficient Execution of Binary Neural Networks Using Resistive Memories

Exploiting Approximate Computing to Increase System Lifetime

Software-Based Self-Test for Transition Faults: a Case Study

Automated Synthesis of Multi-Port Memories and Control

Functional Verification of Hardware Dividers using Algebraic Model

An NBTI-Aware Digital Low-Dropout Regulator with Adaptive Gain Scaling Control

Minimum Energy FinFET Schmitt Trigger Design Considering Process Variability

A Machine Learning-Based Framework for Throughput Estimation of Time-Varying Applications in Multi-Core Servers

A Simplified Layout-Level method for Single Event Transient Faults Susceptibility on Logic Gates

Byte-Aware Floating-point Operations through a UNUM Computing Unit

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