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Technologies Enabling Future Mobile Connectivity and Sensing

1, 2023

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A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

IEEE journal of solid-state circuits, 2016-12, Vol.51 (12), p.3078-3092

2016

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IEEE_Xplore

Charge-based CMOS Digital RF Transmitters

1, 2016

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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

1st ed. 2019., 2019

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Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

IEEE journal of solid-state circuits, 2007-07, Vol.42 (7), p.1501-1512

2007

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IEEE_Xplore

Message From the Outgoing Editor-in-Chief

IEEE journal of solid-state circuits, 2019-08, Vol.54 (8), p.2107-2107

Craninckx, Jan

2019

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IEEE_Xplore

New Associate Editors

IEEE journal of solid-state circuits, 2019-06, Vol.54 (6), p.1515-1516

Craninckx, Jan

2019

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IEEE_Xplore

New Associate Editor

IEEE journal of solid-state circuits, 2018-07, Vol.53 (7), p.1875-1875

Craninckx, Jan

2018

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New Associate Editor

IEEE journal of solid-state circuits, 2018-05, Vol.53 (5), p.1243-1243

Craninckx, Jan

2018

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New Associate Editors

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.963-964

Craninckx, Jan

2018

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IEEE_Xplore

New Associate Editor

IEEE journal of solid-state circuits, 2017-09, Vol.52 (9), p.2223-2223

Craninckx, Jan

2017

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New Associate Editor

IEEE journal of solid-state circuits, 2017-07, Vol.52 (7), p.1699-1699

Craninckx, Jan

2017

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New Associate Editor

IEEE journal of solid-state circuits, 2017-04, Vol.52 (4), p.887-887

Craninckx, Jan

2017

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IEEE_Xplore

50th Anniversary of the Journal

IEEE journal of solid-state circuits, 2016-11, Vol.51 (11), p.2519-2519

Craninckx, Jan

2016

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IEEE_Xplore

Message From the Incoming Editor-in-Chief

IEEE journal of solid-state circuits, 2016-08, Vol.51 (8), p.1732-1732

Craninckx, Jan

2016

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IEEE_Xplore

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

Sensors (Basel, Switzerland), 2018-10, Vol.18 (11), p.3683

2018

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A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2860-2869

2007

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IEEE_Xplore

A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS

IEEE transactions on circuits and systems. I, Regular papers, 2013-04, Vol.60 (4), p.918-925

2013

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IEEE_Xplore

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

IEEE journal of solid-state circuits, 2008-12, Vol.43 (12), p.2693-2705

2008

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IEEE_Xplore

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

IEEE journal of solid-state circuits, 2018-04, Vol.53 (4), p.1161-1171

2018

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IEEE_Xplore

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

IEEE journal of solid-state circuits, 2009-07, Vol.44 (7), p.1942-1949

2009

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IEEE_Xplore

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

IEEE journal of solid-state circuits, 2015-05, Vol.50 (5), p.1203-1213

2015

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IEEE_Xplore

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS

IEEE journal of solid-state circuits, 2019-02, Vol.54 (2), p.403-416

2019

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IEEE_Xplore

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

IEEE journal of solid-state circuits, 2020-12, Vol.55 (12), p.3294-3307

2020

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IEEE_Xplore

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

IEEE journal of solid-state circuits, 2023, p.1-13

2023

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IEEE_Xplore

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Technologies Enabling Future Mobile Connectivity and Sensing

A DTC-Based Subsampling PLL Capable of Self-Calibrated Fractional Synthesis and Two-Point Modulation

Charge-based CMOS Digital RF Transmitters

Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

Message From the Outgoing Editor-in-Chief

New Associate Editors

New Associate Editor

New Associate Editor

New Associate Editors

New Associate Editor

New Associate Editor

New Associate Editor

50th Anniversary of the Journal

Message From the Incoming Editor-in-Chief

Analysis and Design of a CMOS Ultra-High-Speed Burst Mode Imager with In-Situ Storage Topology Featuring In-Pixel CDS Amplification

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

A Digitally Modulated Class-E Polar Amplifier in 90 nm CMOS

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

A 69-dB SNDR 300-MS/s Two-Time Interleaved Pipelined SAR ADC in 16-nm CMOS FinFET With Capacitive Reference Stabilization

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

A 9.2-12.7 GHz Wideband Fractional-N Subsampling PLL in 28 nm CMOS With 280 fs RMS Jitter

A Single-Channel, 600-MS/s, 12-b, Ringamp-Based Pipelined ADC in 28-nm CMOS

A 12-mW 10-GHz FMCW PLL Based on an Integrating DAC With 28-kHz RMS-Frequency-Error for 23-MHz/μs Slope and 1.2-GHz Chirp-Bandwidth

A 16-GHz Background-Calibrated Duty-Cycled FMCW Charge-Pump PLL

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