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Technologies Enabling Future Mobile Connectivity and Sensing

1, 2023

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A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

IEEE journal of solid-state circuits, 1997-05, Vol.32 (5), p.736-744

1997

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Charge-based CMOS Digital RF Transmitters

1, 2016

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Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

1st ed. 2019., 2019

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Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

IEEE journal of solid-state circuits, 2007-07, Vol.42 (7), p.1501-1512

2007

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A 2-mm ^ 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

IEEE journal of solid-state circuits, 2009-12, Vol.44 (12), p.3486-3498

2009

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Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

IEEE journal of solid-state circuits, 2007-07, Vol.42 (7), p.1472-1480

2007

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PLL Modulation and Mixed-Signal Calibration Techniques for FMCW Radar

1, 2024

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A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

IEEE journal of solid-state circuits, 2007-12, Vol.42 (12), p.2860-2869

2007

Volltextzugriff (PDF)

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

IEEE journal of solid-state circuits, 2008-12, Vol.43 (12), p.2693-2705

2008

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A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

IEEE journal of solid-state circuits, 2009-03, Vol.44 (3), p.874-882

2009

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A Design Approach for Power-Optimized Fully Reconfigurable \Delta \Sigma A/D Converter for 4G Radios

IEEE transactions on circuits and systems. II, Express briefs, 2008-03, Vol.55 (3), p.229-233

2008

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A fully integrated CMOS DCS-1800 frequency synthesizer

IEEE journal of solid-state circuits, 1998-12, Vol.33 (12), p.2054-2065

1998

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A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

IEEE journal of solid-state circuits, 2009-07, Vol.44 (7), p.1942-1949

2009

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In-band full-duplex transceiver technology for 5G mobile networks

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.84-87

2015

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A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS

IEEE journal of solid-state circuits, 1996-07, Vol.31 (7), p.890-897

1996

Volltextzugriff (PDF)

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

IEEE journal of solid-state circuits, 2012-12, Vol.47 (12), p.2880-2887

2012

Volltextzugriff (PDF)

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

IEEE journal of solid-state circuits, 1995-12, Vol.30 (12), p.1474-1482

1995

Volltextzugriff (PDF)

A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers

IEEE journal of solid-state circuits, 2011-07, Vol.46 (7), p.1659-1671

2011

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A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer

IEEE journal of solid-state circuits, 2008-02, Vol.43 (2), p.460-467

2008

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A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point

2010 Proceedings of ESSCIRC, 2010, p.402-405

2010

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Direct digital-RF amplitude modulator in CMOS 90nm

Analog integrated circuits and signal processing, 2011-07, Vol.68 (1), p.21-31

2011

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A 6.5-kV ESD-protected 3-5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation

IEEE transactions on microwave theory and techniques, 2006-04, Vol.54 (4), p.1698-1706

2006

Volltextzugriff (PDF)

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$\mu$m CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2008-03, Vol.55 (3), p.224-228

2008

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A fully-integrated single-chip SOC for Bluetooth

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2001, p.196-197

2001

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Technologies Enabling Future Mobile Connectivity and Sensing

A 1.8-GHz low-phase-noise CMOS VCO using optimized hollow spiral inductors

Charge-based CMOS Digital RF Transmitters

Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

Flexible Baseband Analog Circuits for Software-Defined Radio Front-Ends

A 2-mm ^ 0.1-5 GHz Software-Defined Radio Receiver in 45-nm Digital CMOS

Wideband VCO With Simultaneous Switching of Frequency Band, Active Core, and Varactor Size

PLL Modulation and Mixed-Signal Calibration Techniques for FMCW Radar

A 0.65-to-1.4 nJ/Burst 3-to-10 GHz UWB All-Digital TX in 90 nm CMOS for IEEE 802.15.4a

A Compact Wideband Front-End Using a Single-Inductor Dual-Band VCO in 90 nm Digital CMOS

A 2.2 mW 1.75 GS/s 5 Bit Folding Flash ADC in 90 nm Digital CMOS

A Design Approach for Power-Optimized Fully Reconfigurable \Delta \Sigma A/D Converter for 4G Radios

A fully integrated CMOS DCS-1800 frequency synthesizer

A Low-Complexity, Low-Phase-Noise, Low-Voltage Phase-Aligned Ring Oscillator in 90 nm Digital CMOS

In-band full-duplex transceiver technology for 5G mobile networks

A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-μm CMOS

A 1.7 mW 11b 250 MS/s 2-Times Interleaved Fully Dynamic Pipelined SAR ADC in 40 nm Digital CMOS

A 1.8-GHz CMOS low-phase-noise voltage-controlled oscillator with prescaler

A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers

A Polar Modulator Using Self-Oscillating Amplifiers and an Injection-Locked Upconversion Mixer

A sub-3dB NF voltage-sampling front-end with +18dBm IIP3 and +2dBm blocker compression point

Direct digital-RF amplitude modulator in CMOS 90nm

A 6.5-kV ESD-protected 3-5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation

A 100-kHz to 20-MHz Reconfigurable Power-Linearity Optimized $G_m$–$C$ Biquad in 0.13-$\mu$m CMOS

A fully-integrated single-chip SOC for Bluetooth

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