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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

IEEE electron device letters, 2012-09, Vol.33 (9), p.1225-1227

2012

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IEEE_Xplore

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

IEEE electron device letters, 2012-11, Vol.33 (11), p.1526-1528

2012

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IEEE_Xplore

Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

Semiconductor science and technology, 2019-07, Vol.34 (7), p.74001

2019

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Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Solid-state electronics, 2013-06, Vol.84, p.46-52

2013

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Defect analysis of a silicon nanowire transistor by X-ray energy dispersive spectroscopy technique in a STEM: 2D mappings and tomography

Journal of physics. Conference series, 2013-01, Vol.471 (1), p.12027-4

2013

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Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2013, p.300-303

2013

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IEEE_Xplore

Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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IEEE_Xplore

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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IEEE_Xplore

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.121-124

2012

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IEEE_Xplore

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Applied physics letters, 2018-01, Vol.112 (5)

2018

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Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.17.6.1-17.6.4

2016

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IEEE_Xplore

Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Solid-state electronics, 2013-10, Vol.88, p.32-36

2013

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Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.17.2.1-17.2.4

2015

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IEEE_Xplore

Comparative study of circuit perspectives for multi-gate structures at sub-10nm node

Solid-state electronics, 2012-08, Vol.74, p.25-31

2012

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Comparative study of circuit perspectives for multi-gate structures at sub-10ANBnm node

Solid-state electronics, 2012-08, Vol.74, p.25-31

2012

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Comparative study of circuit perspectives for multi-gate structures at sub-10 nm node: Selected Papers from the ESSDERC 2011 Conference

Solid-state electronics, 2012, Vol.74, p.25-31

2012

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Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width

Solid-state electronics, 2013-10, Vol.88, p.32-36

2013

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Scaling of high-Io/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Solid-state electronics, 2013-10, Vol.88, p.32-36

2013

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Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.73-76

2012

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IEEE_Xplore

Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects

2013 Symposium on VLSI Technology, 2013, p.T230-T231

2013

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IEEE_Xplore

Influence of technological and geometrical parameters on low-frequency noise in SOI omega-gate nanowire NMOSFETs

Proceedings of Technical Program - 2014 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2014, p.1-2

2014

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IEEE_Xplore

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width: Selected extended papers from ULIS 2012 conference

Solid-state electronics, 2013, Vol.88, p.32-36

2013

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Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives

2016 IEEE 8th International Memory Workshop (IMW), 2016, p.1-4

2016

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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

Top-down fabrication and electrical characterization of Si and SiGe nanowires for advanced CMOS technologies

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate silicon nanowire MOSFETs

Defect analysis of a silicon nanowire transistor by X-ray energy dispersive spectroscopy technique in a STEM: 2D mappings and tomography

Influence of device scaling on low-frequency noise in SOI tri-gate N- and p-type Si nanowire MOSFETs

Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Scaling of high-kappa/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

Comparative study of circuit perspectives for multi-gate structures at sub-10nm node

Comparative study of circuit perspectives for multi-gate structures at sub-10ANBnm node

Comparative study of circuit perspectives for multi-gate structures at sub-10 nm node: Selected Papers from the ESSDERC 2011 Conference

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10nm width

Scaling of high-Io/metal-gate TriGate SOI nanowire transistors down to 10 nm width

Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor

Study of carrier transport in strained and unstrained SOI tri-gate and omega-gate Si-nanowire MOSFETs

Scaling of Ω-gate SOI nanowire N- and P-FET down to 10nm gate length: Size- and orientation-dependent strain effects

Influence of technological and geometrical parameters on low-frequency noise in SOI omega-gate nanowire NMOSFETs

Scaling of high-κ/metal-gate TriGate SOI nanowire transistors down to 10 nm width: Selected extended papers from ULIS 2012 conference

Vertical CBRAM (V-CBRAM): From Experimental Data to Design Perspectives

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