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Temperature expansions in the square-shoulder fluid. II. Thermodynamics

The Journal of chemical physics, 2020-03, Vol.152 (12), p.124113-124113

2020

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Temperature expansions in the square-shoulder fluid. I. The Wiener–Hopf function

The Journal of chemical physics, 2020-03, Vol.152 (12), p.124112-124112

2020

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Flat phase of quantum polymerized membranes

Physical review. E, 2016-09, Vol.94 (3-1), p.032125-032125, Article 032125

2016

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Glassy phase in quenched disordered crystalline membranes

Physical review. E, 2018-03, Vol.97 (3-1), p.030102-030102, Article 030102

2018

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Universal behaviors in the wrinkling transition of disordered membranes

Physical review. E, 2020-04, Vol.101 (4-1), p.042602-042602, Article 042602

2020

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Spontaneous symmetry breaking and the flat phase of crystalline membranes

Physical review. B, 2019-09, Vol.100 (12), Article 125406

Coquand, O.

2019

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Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

IEEE electron device letters, 2012-09, Vol.33 (9), p.1225-1227

2012

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IEEE_Xplore

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

IEEE electron device letters, 2012-11, Vol.33 (11), p.1526-1528

2012

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IEEE_Xplore

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

IEEE transactions on electron devices, 2013-02, Vol.60 (2), p.727-732

2013

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IEEE_Xplore

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Applied physics letters, 2018-01, Vol.112 (5)

2018

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Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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IEEE_Xplore

Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor

Solid-state electronics, 2013-06, Vol.84, p.179-184

2013

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Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC), 2012, p.121-124

2012

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IEEE_Xplore

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

2012 Symposium on VLSI Technology (VLSIT), 2012, p.13-14

2012

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IEEE_Xplore

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.17.6.1-17.6.4

2016

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IEEE_Xplore

Density Gradient calibration for 2D quantum confinement: Tri-Gate SOI transistor application

2013 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), 2013, p.184-187

2013

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IEEE_Xplore

Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors

2019 IEEE International Electron Devices Meeting (IEDM), 2019, p.11.5.1-11.5.4

2019

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IEEE_Xplore

Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

2013 Symposium on VLSI Technology, 2013, p.T226-T227

2013

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IEEE_Xplore

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

2015 IEEE International Electron Devices Meeting (IEDM), 2015, p.17.2.1-17.2.4

2015

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IEEE_Xplore

NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

2016 IEEE International Electron Devices Meeting (IEDM), 2016, p.7.5.1-7.5.4

2016

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IEEE_Xplore

FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors

2013 IEEE International Electron Devices Meeting, 2013, p.26.4.1-26.4.4

2013

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IEEE_Xplore

Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires

2012 International Electron Devices Meeting, 2012, p.28.1.1-28.1.4

2012

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IEEE_Xplore

300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits

2012 International Electron Devices Meeting, 2012, p.8.7.1-8.7.4

2012

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IEEE_Xplore

Le Corps des Ponts et Chaussées: Histoire de l'administration française

Technology and Culture, 1986, Vol.27 (1), p.145-146

Smith, Cecil O.

1986

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Temperature expansions in the square-shoulder fluid. II. Thermodynamics

Temperature expansions in the square-shoulder fluid. I. The Wiener–Hopf function

Flat phase of quantum polymerized membranes

Glassy phase in quenched disordered crystalline membranes

Universal behaviors in the wrinkling transition of disordered membranes

Spontaneous symmetry breaking and the flat phase of crystalline membranes

Scaling of Trigate Junctionless Nanowire MOSFET With Gate Length Down to 13 nm

Performance of Omega-Shaped-Gate Silicon Nanowire MOSFET With Diameter Down to 8 nm

Strain-Induced Performance Enhancement of Trigate and Omega-Gate Nanowire FETs Scaled Down to 10-nm Width

Strain, stress, and mechanical relaxation in fin-patterned Si/SiGe multilayers for sub-7 nm nanosheet gate-all-around device technology

Scaling of Trigate nanowire (NW) MOSFETs to sub-7 nm width: 300 K transition to Single Electron Transistor

Comparative simulation of TriGate and FinFET on SOI: Evaluating a multiple threshold voltage strategy on triple gate devices

Scaling of Trigate nanowire (NW) MOSFETs to sub-7nm width: 300K transition to Single Electron Transistor

Scaling of Trigate nanowire (NW) MOSFETs Down to 5 nm Width: 300 K transition to Single Electron Transistor, challenges and opportunities

Strain-induced performance enhancement of tri-gate and omega-gate nanowire FETs scaled down to 10nm Width

Vertically stacked-NanoWires MOSFETs in a replacement metal gate process with inner spacer and SiGe source/drain

Density Gradient calibration for 2D quantum confinement: Tri-Gate SOI transistor application

Imaging, Modeling and Engineering of Strain in Gate-All-Around Nanosheet Transitors

Innovative through-Si 3D lithography for ultimate self-aligned planar Double-Gate and Gate-All-Around nanowire transistors

Investigation of the potentialities of Vertical Resistive RAM (VRRAM) for neuromorphic applications

NSP: Physical compact model for stacked-planar and vertical Gate-All-Around MOSFETs

FDSOI nanowires: An opportunity for hybrid circuit with field effect and single electron transistors

Study of piezoresistive properties of advanced CMOS transistors: Thin film SOI, SiGe/SOI, unstrained and strained Tri-Gate Nanowires

300 K operating full-CMOS integrated Single Electron Transistor (SET)-FET circuits

Le Corps des Ponts et Chaussées: Histoire de l'administration française

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