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Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

IEEE transactions on signal processing, 2004-05, Vol.52 (5), p.1315-1326

2004

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Modeling and Hardware Implementation Aspects of Fading Channel Simulators

IEEE transactions on vehicular technology, 2008-07, Vol.57 (4), p.2055-2069

2008

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A Compact Single-FPGA Fading-Channel Simulator

IEEE transactions on circuits and systems. II, Express briefs, 2008-01, Vol.55 (1), p.84-88

2008

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Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

IEEE journal of solid-state circuits, 2007-10, Vol.42 (10), p.2245-2256

2007

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An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems

IEEE transactions on signal processing, 2006-10, Vol.54 (10), p.3899-3907

2006

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A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

IEEE transactions on circuits and systems. I, Regular papers, 2009-05, Vol.56 (5), p.1017-1029

2009

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Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination

IEEE transactions on circuits and systems. I, Regular papers, 2008-12, Vol.55 (11), p.3628-3640

2008

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Design of a 3-D fully depleted SOI computational RAM

IEEE transactions on very large scale integration (VLSI) systems, 2005-03, Vol.13 (3), p.358-369

2005

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Accurate multiple-input multiple-output fading channel simulator using a compact and high-throughput reconfigurable architecture

IET communications, 2011-04, Vol.5 (6), p.844-852

2011

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Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation

IET communications, 2012-03, Vol.6 (5), p.557

2012

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A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions

IEEE transactions on computers, 2010-04, Vol.59 (4), p.449-456

2010

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Improved layered MIMO detection algorithm with near-optimal performance

Electronics letters, 2009, Vol.45 (13), p.675-677

2009

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Compact Rayleigh and Rician fading simulator based on random walk processes

IET communications, 2009-08, Vol.3 (8), p.1333-1342

2009

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Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

IET communications, 2011-06, Vol.5 (9), p.1246-1254

2011

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Layered space-time multiple-input multiple-output detector with parameterisable performance

IET communications, 2012-11, Vol.6 (17), p.3053-3058

2012

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Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-12, Vol.53 (12), p.2595-2605

2006

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FPGA-based accelerator for the verification of leading-edge wireless systems

2009 46th ACM/IEEE Design Automation Conference, 2009, p.844-847

2009

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Efficient implementation of lifting-based discrete wavelet transform

Electronics letters, 2002-08, Vol.38 (18), p.1010-1012

2002

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Hardware-based Error Rate Testing of Digital Baseband Communication Systems

2008 IEEE International Test Conference, 2008, p.1-10

2008

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A flexible layered architecture for accurate digital baseband algorithm development and verification

2009 Design, Automation & Test in Europe Conference & Exhibition, 2009, p.45-50

2009

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A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels

2008 IEEE International Conference on Communications, 2008, p.718-724

2008

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An Accurate and Compact Rayleigh and Rician Fading Channel Simulator

VTC Spring 2008 - IEEE Vehicular Technology Conference, 2008, p.409-413

2008

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An Improved SOS-Based Fading Channel Emulator

2007 IEEE 66th Vehicular Technology Conference, 2007, p.931-935

2007

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Improved Iterative Bit Flipping Decoding Algorithms for LDPC Convolutional Codes

2007 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing, 2007, p.541-544

2007

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Recent developments in dram testing

IEEE International Workshop on Memory Technology, Design and Testing, 1996, p.6-7

Cockburn, B.F.

1996

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Efficient architectures for 1-D and 2-D lifting-based wavelet transforms

Modeling and Hardware Implementation Aspects of Fading Channel Simulators

A Compact Single-FPGA Fading-Channel Simulator

Design and Test of a 175-Mb/s, Rate-1/2 (128,3,6) Low-Density Parity-Check Convolutional Code Encoder and Decoder

An Efficient Parallel Architecture for Implementing LST Decoding in MIMO Systems

A Compact 1.1-Gb/s Encoder and a Memory-Based 600-Mb/s Decoder for LDPC Convolutional Codes

Efficient Implementation of Low-Density Parity-Check Convolutional Code Encoders With Built-In Termination

Design of a 3-D fully depleted SOI computational RAM

Accurate multiple-input multiple-output fading channel simulator using a compact and high-throughput reconfigurable architecture

Accurate simulation of non-isotropic fading channels with arbitrary temporal correlation

A Unified Architecture for the Accurate and High-Throughput Implementation of Six Key Elementary Functions

Improved layered MIMO detection algorithm with near-optimal performance

Compact Rayleigh and Rician fading simulator based on random walk processes

Single-field programmable gate array simulator for geometric multiple-input multiple-output fading channel models

Layered space-time multiple-input multiple-output detector with parameterisable performance

Using Stacked Bitlines and Hybrid ROM Cells to Form ROM and SRAM-ROM With Increased Storage Density

FPGA-based accelerator for the verification of leading-edge wireless systems

Efficient implementation of lifting-based discrete wavelet transform

Hardware-based Error Rate Testing of Digital Baseband Communication Systems

A flexible layered architecture for accurate digital baseband algorithm development and verification

A Novel Technique for Efficient Hardware Simulation of Spatiotemporally Correlated MIMO Fading Channels

An Accurate and Compact Rayleigh and Rician Fading Channel Simulator

An Improved SOS-Based Fading Channel Emulator

Improved Iterative Bit Flipping Decoding Algorithms for LDPC Convolutional Codes

Recent developments in dram testing

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