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Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

IEEE microwave and wireless components letters, 2007-12, Vol.17 (12), p.855-857

2007

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A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

IEEE microwave and wireless components letters, 2009-08, Vol.19 (8), p.512-514

2009

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A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

IEEE microwave and wireless components letters, 2006-12, Vol.16 (12), p.651-653

2006

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Field source extraction of an ESD generator and its application to system-level ESD analysis in a solid-state storage system

Journal of electromagnetic waves and applications, 2021-06, Vol.35 (9), p.1247-1260

2021

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Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

IEEE journal of solid-state circuits, 2006-01, Vol.41 (1), p.274-286

2006

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Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning

IEEE transactions on signal and power integrity, 2023-01, Vol.2, p.1-13

2023

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Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

2007 International Conference on Electronic Materials and Packaging, 2007, p.1-6

2007

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Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

IEEE transactions on advanced packaging, 2008-08, Vol.31 (3), p.544-557

2008

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Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

2007 Proceedings 57th Electronic Components and Technology Conference, 2007, p.847-852

2007

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High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

2006 1st Electronic Systemintegration Technology Conference, 2006, Vol.1, p.215-220

2006

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A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005, 2005, p.514-614 Vol. 1

2005

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Development of an ESD Risk Evaluation Method for SSD Installation in Host Systems

2024 International Symposium on Electromagnetic Compatibility – EMC Europe, 2024, p.1064-1069

2024

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A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design

2010 Asia-Pacific International Symposium on Electromagnetic Compatibility, 2010, p.334-337

2010

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Optimal Power Distribution Network Design for High-Performance Solid-State-Drive Based on Novel Target-Impedance Extraction Method

2021 IEEE International Joint EMC/SI/PI and EMC Europe Symposium, 2021, p.163-167

2021

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Jitter suppressed on-chip clock distribution using package plane cavity resonance

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008, p.427-430

2008

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Effect of power distribution network design on RF circuit performance for 900MHz RFID reader

2006 8th Electronics Packaging Technology Conference, 2006, p.860-865

2006

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A frequency tunable resonant clock distribution scheme using bond-wire inductor

2008 Electrical Design of Advanced Packaging and Systems Symposium, 2008, p.24-26

2008

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Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

2008 Asia-Pacific Symposium on Electromagnetic Compatibility and 19th International Zurich Symposium on Electromagnetic Compatibility, 2008, p.351-354

2008

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An On-die Oscilloscope for System-Level ESD Noise Monitoring

2019 IEEE International Symposium on Electromagnetic Compatibility, Signal & Power Integrity (EMC+SIPI), 2019, p.156-160

2019

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Analysis of the Effect of AC Noise on DC Bias of VGA for UHF RFID using Chip-package Co-modeling and Simulation

2007 9th Electronics Packaging Technology Conference, 2007, p.591-594

2007

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Effect of EBG Structures for Reducing Noise in Multi-Layer PCBs for Digital Systems

2006 IEEE Electrical Performane of Electronic Packaging, 2006, p.253-256

2006

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Estimation of Data-Dependent Jitter Using Single Pulse Analysis Method in High-Speed Differential Signaling

2006 1st Electronic Systemintegration Technology Conference, 2006, Vol.2, p.741-746

2006

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Analysis of the Effect of Digital Power Ground Noise on Active Balun in UHF RFID SiP

2007 9th Electronics Packaging Technology Conference, 2007, p.586-590

2007

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High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

IEEE 14th Topical Meeting on Electrical Performance of Electronic Packaging, 2005, 2005, p.151-154

2005

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Data-dependent jitter estimation using single pulse analysis method

2005 7th Electronic Packaging Technology Conference, 2005, Vol.2, p.4 pp.

2005

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Suppression of Power/Ground Inductive Impedance and Simultaneous Switching Noise Using Silicon Through-Via in a 3-D Stacked Chip Package

A 3-D Low Jitter and Skew Clock Distribution Network Scheme Using LTCC Package Level Interposer With a Planar Cavity Resonator

A Three-Dimensional Stacked-Chip Star-Wiring Interconnection for a Digital Noise-Free and Low-Jitter I/O Clock Distribution Network

Field source extraction of an ESD generator and its application to system-level ESD analysis in a solid-state storage system

Chip-package hybrid clock distribution network and DLL for low jitter clock delivery

Novel Target-Impedance Extraction Method-Based Optimal PDN Design for High-Performance SSD Using Deep Reinforcement Learning

Electrical characterization of trough silicon via (TSV) depending on structural and material parameters based on 3D full wave simulation

Modeling and Measurement of Interlevel Electromagnetic Coupling and Fringing Effect in a Hierarchical Power Distribution Network Using Segmentation Method With Resonant Cavity Model

Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)

High Frequency Electrical Model of Through Wafer Via for 3-D Stacked Chip Packaging

A chip-package hybrid DLL loop and clock distribution network for low-jitter clock delivery

Development of an ESD Risk Evaluation Method for SSD Installation in Host Systems

A designated clock generation and distribution (DCGD) chip scheme for substrate noise-free 3-D stacked SiP design

Optimal Power Distribution Network Design for High-Performance Solid-State-Drive Based on Novel Target-Impedance Extraction Method

Jitter suppressed on-chip clock distribution using package plane cavity resonance

Effect of power distribution network design on RF circuit performance for 900MHz RFID reader

A frequency tunable resonant clock distribution scheme using bond-wire inductor

Wideband low power distribution network impedance of high chip density package using 3-D stacked through silicon vias

An On-die Oscilloscope for System-Level ESD Noise Monitoring

Analysis of the Effect of AC Noise on DC Bias of VGA for UHF RFID using Chip-package Co-modeling and Simulation

Effect of EBG Structures for Reducing Noise in Multi-Layer PCBs for Digital Systems

Estimation of Data-Dependent Jitter Using Single Pulse Analysis Method in High-Speed Differential Signaling

Analysis of the Effect of Digital Power Ground Noise on Active Balun in UHF RFID SiP

High frequency electrical circuit model of chip-to-chip vertical via interconnection for 3-D chip stacking package

Data-dependent jitter estimation using single pulse analysis method

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