UB Paderborn / Katalog / Suche / in CDI

A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery

Sensors (Basel, Switzerland), 2023-11, Vol.23 (23), p.9437

2023

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Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles

Sensors (Basel, Switzerland), 2024-04, Vol.24 (7), p.2265

2024

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CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis

Sensors (Basel, Switzerland), 2023-06, Vol.23 (13), p.5897

2023

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A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis

IEEE transactions on instrumentation and measurement, 2024, Vol.73, p.1-11

2024

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A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

IEEE transactions on very large scale integration (VLSI) systems, 2016-01, Vol.24 (1), p.408-412

2016

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An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring

IEEE transactions on circuits and systems. II, Express briefs, 2011-02, Vol.58 (2), p.105-109

2011

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A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology

IEEE journal of solid-state circuits, 2011-10, Vol.46 (10), p.2300-2311

2011

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A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

IEEE transactions on very large scale integration (VLSI) systems, 2015-11, Vol.23 (11), p.2487-2496

2015

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An all-digital phase-locked loop for high-speed clock generation

IEEE journal of solid-state circuits, 2003-02, Vol.38 (2), p.347-351

2003

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A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

IEEE transactions on very large scale integration (VLSI) systems, 2015-05, Vol.23 (5), p.983-987

2015

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High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

IEEE transactions on very large scale integration (VLSI) systems, 2014-05, Vol.22 (5), p.1096-1105

2014

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An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

IEEE transactions on circuits and systems. II, Express briefs, 2007-11, Vol.54 (11), p.954-958

2007

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A Low-Power DCO Using Interlaced Hysteresis Delay Cells

IEEE transactions on circuits and systems. II, Express briefs, 2012-10, Vol.59 (10), p.673-677

2012

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A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems

IEEE transactions on circuits and systems. I, Regular papers, 2022-09, Vol.69 (9), p.3816-3828

2022

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A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications

IEEE transactions on very large scale integration (VLSI) systems, 2011-06, Vol.19 (6), p.1113-1117

2011

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A portable digitally controlled oscillator using novel varactors

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2005-05, Vol.52 (5), p.233-237

2005

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Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID

IEEE transactions on very large scale integration (VLSI) systems, 2014-07, Vol.22 (7), p.1470-1480

2014

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Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2011-03, Vol.58 (3), p.149-153

2011

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A new DLL-based approach for all-digital multiphase clock generation

IEEE journal of solid-state circuits, 2004-03, Vol.39 (3), p.469-475

2004

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A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

IEEE journal of solid-state circuits, 2006-06, Vol.41 (6), p.1275-1285

2006

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An All-Digital Large- N Audio Frequency Synthesizer for HDMI Applications

IEEE transactions on circuits and systems. II, Express briefs, 2012-07, Vol.59 (7), p.424-428

2012

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An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling

2013 IEEE International Symposium on Circuits and Systems (ISCAS), 2013, p.2682-2685

2013

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A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

IEEE transactions on circuits and systems. II, Express briefs, 2008-09, Vol.55 (9), p.922-926

2008

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A cell-based 5-MHz on-chip clock generator

Elektrik : Turkish journal of electrical engineering & computer sciences, 2017, Vol.25, p.1472-1482

2017

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An area-efficient and wide-range digital DLL for per-pin deskew applications

Elektrik : Turkish journal of electrical engineering & computer sciences, 2017, Vol.25, p.2185-2194

2017

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A Multiplier-Free Convolution Neural Network Hardware Accelerator for Real-Time Bearing Condition Detection of CNC Machinery

Implementation of Lightweight Convolutional Neural Networks with an Early Exit Mechanism Utilizing 40 nm CMOS Process for Fire Detection in Unmanned Aerial Vehicles

CNN Hardware Accelerator for Real-Time Bearing Fault Diagnosis

A Low-Power Hierarchical CNN Hardware Accelerator for Bearing Fault Diagnosis

A 0.52/1 V Fast Lock-in ADPLL for Supporting Dynamic Voltage and Frequency Scaling

An Autocalibrated All-Digital Temperature Sensor for On-Chip Thermal Monitoring

A Fast Phase Tracking ADPLL for Video Pixel Clock Generation in 65 nm CMOS Technology

A Wide-Range Low-Cost All-Digital Duty-Cycle Corrector

An all-digital phase-locked loop for high-speed clock generation

A Low-Cost Low-Power All-Digital Spread-Spectrum Clock Generator

High-Resolution All-Digital Duty-Cycle Corrector in 65-nm CMOS Technology

An Ultra-Low-Power and Portable Digitally Controlled Oscillator for SoC Applications

A Low-Power DCO Using Interlaced Hysteresis Delay Cells

A Maximum Logarithmic Maximum a Posteriori Probability Based Soft-Input Soft-Output Detector for the Coded Spatial Modulation Systems

A Low-Power and Portable Spread Spectrum Clock Generator for SoC Applications

A portable digitally controlled oscillator using novel varactors

Partial Parity Cache and Data Cache Management Method to Improve the Performance of an SSD-Based RAID

Built-in Self-Calibration Circuit for Monotonic Digitally Controlled Oscillator Design in 65-nm CMOS Technology

A new DLL-based approach for all-digital multiphase clock generation

A clock generator with cascaded dynamic frequency counting loops for wide multiplication range applications

An All-Digital Large- N Audio Frequency Synthesizer for HDMI Applications

An all-digital on-chip silicon oscillator with automatic VT range selection relative modeling

A Symbol-Rate Timing Synchronization Method for Low Power Wireless OFDM Systems

A cell-based 5-MHz on-chip clock generator

An area-efficient and wide-range digital DLL for per-pin deskew applications

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