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( 1 / 3 ) A VDD -to- ( 3 / 2 ) A VDD Wide-Range I/O Buffer Using 0.35- mu m 3.3-V CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2010-02, Vol.57 (2), p.126-130

2010

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(1/3) \times \hbox-to- (3/2) \times \hbox Wide-Range I/O Buffer Using 0.35- \mu\hbox 3.3-V CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2010-02, Vol.57 (2), p.126-130

2010

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(1/3)VDD-to- (3/2) VDD Wide-Range I/O Buffer Using 0.35- km 3.3-V CMOS Technology

IEEE transactions on circuits and systems. II, Express briefs, 2010-02, Vol.57 (2), p.126-130

2010

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A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

Microelectronics, 2024-09, Vol.151, p.106355, Article 106355

2024

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1.8 V to 5.0 V mixed-voltage-tolerant I/O buffer with 54.59% output duty cycle

2008 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), 2008, p.93-96

2008

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A 10-bit 400-MS/s current-steering DAC with process calibration

2013 IEEE International Conference on Circuits and Systems (ICCAS), 2013, p.23-26

2013

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A 10-bit 50-MS/s SAR ADC with Split-Capacitor Array Using Unity-Gain Amplifiers Applied in FOG Systems

2021 IEEE 4th International Conference on Electronics Technology (ICET), 2021, p.356-359

2021

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A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder

Circuits, systems, and signal processing, 2023-04, Vol.42 (4), p.2283-2304

2023

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2.45 GHz ZigBee receiver frontend for HAN with smart meter

2011 International Symposium on Integrated Circuits, 2011, p.480-483

2011

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A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), 2021, p.153-156

2021

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A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

2023 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), 2023, p.271-275

2023

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A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems

International journal of electronics, 2023-11, Vol.110 (11), p.1938-1956

2023

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2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Circuits, systems, and signal processing, 2021-06, Vol.40 (6), p.2824-2840

2021

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2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

2017 7th International Conference on Integrated Circuits, Design, and Verification (ICDV), 2017, p.22-27

2017

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2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

Circuits, systems, and signal processing, 2021-06, Vol.40 (6), p.2824-2840

2021

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A 2×VDD output buffer with PVT detector for slew rate compensation

Microelectronics, 2013-05, Vol.44 (5), p.393-399

2013

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A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology

2021 IEEE Asia Pacific Conference on Circuit and Systems (APCCAS), 2021, p.33-36

2021

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20 MHz accurate peak detector for FPW allergy biosensor with digital calibration

2011 International Symposium on Integrated Circuits, 2011, p.476-479

2011

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20V HV Energy Harvesting Circuit with ACC/CV Mode and MPPT Control for a 5 W Solar Panel

2020 2nd International Conference on Smart Power & Internet Energy Systems (SPIES), 2020, p.205-208

2020

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2xVDD digital output buffer insensitive to process and voltage variations

2017 IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics (PrimeAsia), 2017, p.29-32

2017

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A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process

Integration (Amsterdam), 2023-05, Vol.90, p.245-260

2023

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A 2XVDD output buffer with PVT detector for slew rate compensation

Microelectronics, 2013-05, Vol.44 (5), p.393-399

2013

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A ±3.07% frequency variation clock generator implemented using HV CMOS process

Microelectronics, 2015-04, Vol.46 (4), p.285-290

2015

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A 30 V rail-to-rail operational amplifier

Microelectronics, 2015-10, Vol.46 (10), p.911-915

2015

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A 30V rail-to-rail operational amplifier

Microelectronics, 2015-10, Vol.46 (10), p.911-915

2015

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( 1 / 3 ) A VDD -to- ( 3 / 2 ) A VDD Wide-Range I/O Buffer Using 0.35- mu m 3.3-V CMOS Technology

(1/3) \times \hbox-to- (3/2) \times \hbox Wide-Range I/O Buffer Using 0.35- \mu\hbox 3.3-V CMOS Technology

(1/3)VDD-to- (3/2) VDD Wide-Range I/O Buffer Using 0.35- km 3.3-V CMOS Technology

A 1–6.5 Gbps dual-loop CDR design with Coarse-fine Tuning VCO and modified DQFD

1.8 V to 5.0 V mixed-voltage-tolerant I/O buffer with 54.59% output duty cycle

A 10-bit 400-MS/s current-steering DAC with process calibration

A 10-bit 50-MS/s SAR ADC with Split-Capacitor Array Using Unity-Gain Amplifiers Applied in FOG Systems

A 16-nm FinFET 28.8-mW 800-MHz 8-Bit All-N-Transistor Logic Carry Look-Ahead Adder

2.45 GHz ZigBee receiver frontend for HAN with smart meter

A 2.5-GHz 2×VDD 16-nm FinFET Digital Output Buffer with Slew Rate and Duty Cycle Self-Adjustment

A 2.6-GHz I/O Buffer for DDR4 & DDR5 SDRAMs in 16-nm FinFET CMOS Process

A 2.71 fJ/conversion-step 10-bit 50 MSPS split-capacitor array SAR ADC for FOG systems

2$$\times $$VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

2 × VDD 28-nm CMOS digital output buffer using low-Vth transistors for slew rate adjustment

2×VDD 500 MHz Digital Output Buffer with Optimal Driver Transistor Sizing for Slew Rate Self-adjustment and Leakage Reduction Using 28-nm CMOS Process

A 2×VDD output buffer with PVT detector for slew rate compensation

A 20 GHz 8-bit All-N-Transistor Logic CLA Using 16-nm FinFET Technology

20 MHz accurate peak detector for FPW allergy biosensor with digital calibration

20V HV Energy Harvesting Circuit with ACC/CV Mode and MPPT Control for a 5 W Solar Panel

2xVDD digital output buffer insensitive to process and voltage variations

A 2xVDD digital output buffer with gate driving stability and non-overlapping signaling control for slew-rate auto-adjustment using 16-nm FinFET CMOS process

A 2XVDD output buffer with PVT detector for slew rate compensation

A ±3.07% frequency variation clock generator implemented using HV CMOS process

A 30 V rail-to-rail operational amplifier

A 30V rail-to-rail operational amplifier

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