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A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

IEEE journal of solid-state circuits, 2015-11, Vol.50 (11), p.2603-2612

2015

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A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS

IEEE transactions on circuits and systems. II, Express briefs, 2020-10, Vol.67 (10), p.1834-1838

2020

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An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

IEEE transactions on circuits and systems. II, Express briefs, 2015-09, Vol.62 (9), p.836-840

2015

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A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

IEEE transactions on circuits and systems. II, Express briefs, 2014-05, Vol.61 (5), p.304-308

2014

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A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

ESSCIRC Conference 2015 - 41st European Solid-State Circuits Conference (ESSCIRC), 2015, p.384-387

2015

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A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

IEEE transactions on circuits and systems. II, Express briefs, 2017-12, Vol.64 (12), p.1432-1436

2017

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A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias

IEEE journal of solid-state circuits, 2016-10, Vol.51 (10), p.2312-2327

2016

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An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

2015 Symposium on VLSI Circuits (VLSI Circuits), 2015, p.C136-C137

2015

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A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015, p.1-4

2015

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A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

2018 IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), 2018, p.263-266

2018

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A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process

2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2014, p.101-104

2014

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6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

2020 IEEE International Solid- State Circuits Conference - (ISSCC), 2020, p.122-124

2020

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A 22 to 26.5 Gb/s Optical Receiver With All-Digital Clock and Data Recovery in a 65 nm CMOS Process

A Programmable On-Chip Reference Oscillator With Slow-Wave Coplanar Waveguide in 14-nm FinFET CMOS

An Optimum Loop Gain Tracking All-Digital PLL Using Autocorrelation of Bang-Bang Phase-Frequency Detection

A Four-Channel 32-Gb/s Transceiver With Current-Recycling Output Driver and On-Chip AC Coupling in 65-nm CMOS Process

A 5-GHz subharmonically injection-locked all-digital PLL with complementary switched injection

A 55.1 mW 1.62-to-8.1 Gb/s Video Interface Receiver Generating up to 680 MHz Stream Clock Over 20 dB Loss Channel

A 20 Gb/s 0.4 pJ/b Energy-Efficient Transmitter Driver Utilizing Constant- Bias

An all-digital bang-bang PLL using two-point modulation and background gain calibration for spread spectrum clock generation

A 20 Gb/s 0.4 pJ/b energy-efficient transmitter driver architecture utilizing constant Gm

A Crystal-Less Programmable Clock Generator with RC-LC Hybrid Oscillator for GHz Applications in 14 nm FinFET CMOS

A 26.5 Gb/s optical receiver with all-digital clock and data recovery in 65nm CMOS process

6.4 A 56Gb/s 7.7mW/Gb/s PAM-4 Wireline Transceiver in 10nm FinFET Using MM-CDR-Based ADC Timing Skew Control and Low-Power DSP with Approximate Multiplier

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