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A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

Analog integrated circuits and signal processing, 2016-12, Vol.89 (3), p.561-573

2016

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A 1.25mW 0.8-28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

2015 IEEE International Symposium on Circuits and Systems (ISCAS), 2015, p.549-552

2015

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Coupled inductor, constant resistance, broadband delay filter

Analog integrated circuits and signal processing, 2008, Vol.54 (1), p.7-20

Choma, John

2008

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Nonlinear Cognitive Signal Processing in Ultralow-Power Programmable Analog Hardware

IEEE transactions on circuits and systems. II, Express briefs, 2015-02, Vol.62 (2), p.124-128

2015

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A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

IEEE journal of solid-state circuits, 2001-10, Vol.36 (10), p.1453-1463

2001

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Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

IEEE transactions on circuits and systems. 1, Fundamental theory and applications, 2006-10, Vol.53 (10), p.2101-2108

2006

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New monolithic variable capacitor

Analog integrated circuits and signal processing, 2001-02, Vol.26 (2), p.89-102

2001

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New monolithic voltage-controlled oscillator

Analog integrated circuits and signal processing, 2001-02, Vol.26 (2), p.103-115

2001

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Low power false positive tolerant event detector for seismic sensors

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), 2013, p.1-2

2013

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A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2000-04, Vol.47 (4), p.363-369

2000

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A reduced delay method for improving the performance of sigma-delta analog-to-digital converters (ADC)

Analog integrated circuits and signal processing, 2002-03, Vol.30 (3), p.207-215

2002

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A charge transfer-based high performance, ultra-low power PLL charge pump

2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS), 2015, p.1-4

2015

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CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009, p.180-183

2009

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How About the Role of Circuit Analysis?

Journal of Electrical & Electronics, 2012, Vol.1 (1)

Choma, John

2012

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A 9-nW on-chip constant subthreshold CMOS transconductance bias with fine-tuning

2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017, p.1-4

2017

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Large signal modeling of HBT's including self-heating and transit time effects

IEEE transactions on microwave theory and techniques, 1992-03, Vol.40 (3), p.449-464

1992

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CMOS charge-metering microstimulator for implantable prosthetic device

2008 51st Midwest Symposium on Circuits and Systems, 2008, p.826-829

2008

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A dynamic thermal management circuit for system-on-chip designs

Analog integrated circuits and signal processing, 2003-07, Vol.36 (1-2), p.175-181

2003

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A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier

2007 IEEE International Symposium on Circuits and Systems (ISCAS), 2007, p.337-340

2007

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CAS 101 [electronic engineering education]

IEEE circuits and devices magazine, 1998-05, Vol.14 (3), p.16-22

Choma, J.

1998

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40nW subthreshold event detector chip for seismic sensors

2015 IEEE International Symposium on Technologies for Homeland Security (HST), 2015, p.1-6

2015

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A capacitively phase-coupled low noise, low power 0.8-to-28.2GHz quadrature ring VCO in 40nm CMOS

2015 IEEE 13th International New Circuits and Systems Conference (NEWCAS), 2015, p.1-4

2015

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A CMOS monolithic image-reject filter

Analog integrated circuits and signal processing, 2001-07, Vol.28 (1), p.43-51

2001

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Low power, long life design for smart intelligence, surveillance, and reconnaissance (ISR) sensors

2012 IEEE Conference on Technologies for Homeland Security (HST), 2012, p.631-636

2012

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Supply noise insensitive PLL design through PWL behavioral modeling and simulation

IEEE transactions on circuits and systems. 2, Analog and digital signal processing, 2001-12, Vol.48 (12), p.1137-1144

2001

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A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

A 1.25mW 0.8-28.2GHz charge pump PLL with 0.82ps RMS jitter in all-digital 40nm CMOS

Coupled inductor, constant resistance, broadband delay filter

Nonlinear Cognitive Signal Processing in Ultralow-Power Programmable Analog Hardware

A supply-noise-insensitive CMOS PLL with a voltage regulator using DC-DC capacitive converter

Architecture and Implementation of a Low-Power LVDS Output Buffer for High-Speed Applications

New monolithic variable capacitor

New monolithic voltage-controlled oscillator

Low power false positive tolerant event detector for seismic sensors

A continuous-time common-mode feedback circuit (CMFB) for high-impedance current-mode applications

A reduced delay method for improving the performance of sigma-delta analog-to-digital converters (ADC)

A charge transfer-based high performance, ultra-low power PLL charge pump

CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC

How About the Role of Circuit Analysis?

A 9-nW on-chip constant subthreshold CMOS transconductance bias with fine-tuning

Large signal modeling of HBT's including self-heating and transit time effects

CMOS charge-metering microstimulator for implantable prosthetic device

A dynamic thermal management circuit for system-on-chip designs

A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS Amplifier

CAS 101 [electronic engineering education]

40nW subthreshold event detector chip for seismic sensors

A capacitively phase-coupled low noise, low power 0.8-to-28.2GHz quadrature ring VCO in 40nm CMOS

A CMOS monolithic image-reject filter

Low power, long life design for smart intelligence, surveillance, and reconnaissance (ISR) sensors

Supply noise insensitive PLL design through PWL behavioral modeling and simulation

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