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PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.336-348

2015

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A scalable processing-in-memory accelerator for parallel graph processing

2015 ACM/IEEE 42nd Annual International Symposium on Computer Architecture (ISCA), 2015, p.105-117

2015

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IEEE_Xplore

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.1393-1398

2016

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IEEE_Xplore

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

IEEE transactions on computers, 2016-03, Vol.65 (3), p.940-951

2016

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IEEE_Xplore

IL-21-mediated reversal of NK cell exhaustion facilitates anti-tumour immunity in MHC class I-deficient tumours

Nature communications, 2017-06, Vol.8 (1), p.15776-15776, Article 15776

2017

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Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

2016 53nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2016, p.1-6

2016

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An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding

IEEE transactions on computer-aided design of integrated circuits and systems, 2018-12, Vol.37 (12), p.3056-3066

2018

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IEEE_Xplore

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping

IPSJ Transactions on System LSI Design Methodology, 2011, Vol.4, pp.31-46

Choi, Kiyoung

2011

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Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks

2017 IEEE International Conference on Computer Design (ICCD), 2017, p.105-112

2017

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IEEE_Xplore

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

IEEE transactions on very large scale integration (VLSI) systems, 2018-01, Vol.26 (1), p.37-49

2018

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Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip

IET computers & digital techniques, 2016-01, Vol.10 (1), p.37-44

2016

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Sternoclavicular xanthogranulomatous osteomyelitis in a patient after kidney transplantation: a case report

Clinical Transplantation and Research, 2024, 38(2), , pp.150-153

2024

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Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching

IEEE transactions on very large scale integration (VLSI) systems, 2016-02, Vol.24 (2), p.453-464

2016

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IEEE_Xplore

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures

IEEE transactions on computer-aided design of integrated circuits and systems, 2011-05, Vol.30 (5), p.637-650

2011

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IEEE_Xplore

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

IEEE transactions on very large scale integration (VLSI) systems, 2014-05, Vol.22 (5), p.1197-1201

2014

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IEEE_Xplore

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

2014 IEEE 20th International Symposium on High Performance Computer Architecture (HPCA), 2014, p.25-36

2014

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IEEE_Xplore

Design space exploration of FPGA accelerators for convolutional neural networks

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017, p.1147-1152

2017

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IEEE_Xplore

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares

IEEE transactions on very large scale integration (VLSI) systems, 2017-06, Vol.25 (6), p.1793-1806

2017

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IEEE_Xplore

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization

IEEE transactions on computer-aided design of integrated circuits and systems, 2013-01, Vol.32 (1), p.34-46

2013

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IEEE_Xplore

High-Level Synthesis: Productivity, Performance, and Software Constraints

Journal of Electrical and Computer Engineering, 2012-01, Vol.2012 (1)

2012

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Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, p.1-6

2014

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Exploiting New Interconnect Technologies in On-Chip Communication

IEEE journal on emerging and selected topics in circuits and systems, 2012-06, Vol.2 (2), p.124-136

2012

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IEEE_Xplore

Active Memory Processor for Network-on-Chip-Based Architecture

IEEE transactions on computers, 2012-05, Vol.61 (5), p.622-635

2012

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IEEE_Xplore

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic

2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2016, p.1243-1248

2016

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IEEE_Xplore

Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture

IEEE transactions on very large scale integration (VLSI) systems, 2010-10, Vol.18 (10), p.1471-1482

2010

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IEEE_Xplore

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PIM-enabled instructions: a low-overhead, locality-aware processing-in-memory architecture

A scalable processing-in-memory accelerator for parallel graph processing

Efficient FPGA acceleration of Convolutional Neural Networks using logical-3D compute array

Prediction Hybrid Cache: An Energy-Efficient STT-RAM Cache Architecture

IL-21-mediated reversal of NK cell exhaustion facilitates anti-tumour immunity in MHC class I-deficient tumours

Dynamic energy-accuracy trade-off using stochastic computing in deep neural networks

An Efficient and Accurate Stochastic Number Generator Using Even-Distribution Coding

Coarse-Grained Reconfigurable Array: Architecture and Application Mapping

Accurate and Efficient Stochastic Computing Hardware for Convolutional Neural Networks

Delay Monitoring System With Multiple Generic Monitors for Wide Voltage Range Operation

Adaptively weighted round-robin arbitration for equality of service in a many-core network-on-chip

Sternoclavicular xanthogranulomatous osteomyelitis in a patient after kidney transplantation: a case report

Low-Power Hybrid Memory Cubes With Link Power Management and Two-Level Prefetching

Mapping Multi-Domain Applications Onto Coarse-Grained Reconfigurable Architectures

LASIC: Loop-Aware Sleepy Instruction Caches Based on STT-RAM Technology

DASCA: Dead Write Prediction Assisted STT-RAM Cache Architecture

Design space exploration of FPGA accelerators for convolutional neural networks

Excavating the Hidden Parallelism Inside DRAM Architectures With Buffered Compares

Isomorphism-Aware Identification of Custom Instructions With I/O Serialization

High-Level Synthesis: Productivity, Performance, and Software Constraints

Dynamic Power Management of Off-Chip Links for Hybrid Memory Cubes

Exploiting New Interconnect Technologies in On-Chip Communication

Active Memory Processor for Network-on-Chip-Based Architecture

Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic

Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture

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