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Temperature Dependence of Substrate and Drain-Currents in Bulk FinFETs

IEEE transactions on electron devices, 2007-05, Vol.54 (5), p.1259-1264

2007

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Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

IEEE transactions on electron devices, 2007-03, Vol.54 (3), p.537-545

2007

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Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal--Oxide--Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

Japanese Journal of Applied Physics, 2010-10, Vol.49 (10), p.104201-104201-6

2010

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Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering

Japanese Journal of Applied Physics, 2008-05, Vol.47 (5R), p.3396

2008

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Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function

Japanese Journal of Applied Physics, 2008-06, Vol.47 (6R), p.4385

2008

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Current--Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

Japanese Journal of Applied Physics, 2013-06, Vol.52 (6), p.064202-064202-8

2013

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Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

Japanese Journal of Applied Physics, 2006-03, Vol.45 (3R), p.1467

2006

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Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions

Japanese Journal of Applied Physics, 2009-08, Vol.48 (8), p.84501

2009

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Comparison of SOI FinFETs and Bulk FinFETs

ECS transactions, 2009, Vol.19 (4), p.101-112

2009

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Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias

Japanese Journal of Applied Physics, 2009-05, Vol.48 (5R), p.54503

2009

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Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel

Japanese Journal of Applied Physics, 2008-11, Vol.47 (11R), p.8253

2008

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Design of NAND Flash Memory Device by the Fringing Field from a Control Gate

Journal of the Korean Physical Society, 2008, 53(6), , pp.3411-3415

2008

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Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

IEEE transactions on nanotechnology, 2008-07, Vol.7 (4), p.427-433

2008

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Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Journal of the Korean Physical Society, 2007, 51(III), , pp.275-279

2007

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Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Japanese Journal of Applied Physics, 2007-06, Vol.46 (6R), p.3347

2007

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Programming/Erasing Characteristics of 45 nm NOR-Type Flash Memory Based on SOI FinFET Structure

Journal of the Korean Physical Society, 2005, 47(3), , pp.564-567

2005

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Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Japanese Journal of Applied Physics, 2005-04, Vol.44 (4S), p.2176

2005

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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Journal of semiconductor technology and science, 2007-06, Vol.7 (2), p.76-81

2007

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A Study on the Utilization of Color Theories in Kurt Schwitters’ Collages

Journal of the Association of Western Art History, 2021-08, Vol.55, p.75-96

Choi, Byung Kil

2021

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A Study on the Structural Transformation of Composition and Its Aesthetics in Roy Lichtenstein’s Early Pop Comic Strips(1961-65)

Europe Culture Arts Association, 2021-03, Vol.12 (1), p.25-52

Choi, Byung-kil

2021

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Deleuze’s Anti-Platonist Concepts : Its Possibility as Tool for the Interpretation of Modern Art

Journal of Basic Design & Art, 2021-02, Vol.22 (1), p.381-394

Choi, Byung Kil

2021

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A Study on Men’s Hair Styles and Their Plastic Beauty in Goguryeo Tomb Murals - Focused on the Relations with China and Changing Process

Korean Chinese Relations Review, 2020-10, Vol.6 (3), p.167-194

Choi, Byung Kil

2020

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Threshold-Voltage Modeling of Bulk FinFETs by Considering Charge-Sharing and Surface Potential

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007, p.19-24

2007

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Interpretation of Picasso's Collages by R. E. Krauss and T. J. Clark's Views of Radical Art History

Journal of Basic Design & Art, 2018-04, Vol.19 (2), p.521-532

Choi, Byung Kil

2018

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Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

Journal of semiconductor technology and science, 2007, Vol.7 (2), p.76-81

2007

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Temperature Dependence of Substrate and Drain-Currents in Bulk FinFETs

Threshold-Voltage Modeling of Body-Tied FinFETs (Bulk FinFETs)

Analytic Oxide Capacitance Model of Double- and Surrounding-Gate Metal--Oxide--Semiconductor Field-Effect Transistors in Linear Region by Considering Inversion-Layer Capacitance

Threshold-Voltage Modeling of Bulk Fin Field Transistors by Considering Surface Potential Lowering

Design of Bulk Fin-Type Field-Effect Transistor Considering Gate Work-Function

Current--Voltage Model of Bulk Fin Field-Effect Transistors with a Half-Circle Corner

Negative Bias Temperature Instability of Bulk Fin Field Effect Transistor

Current Model of Fully Depleted Nanoscale Surrounding-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel in All Operation Regions

Comparison of SOI FinFETs and Bulk FinFETs

Threshold Voltage Modeling of Fully Depleted Nanoscale Double-Gate Metal–Oxide–Semiconductor Field-Effect Transistors with Doped Channel by Considering Drain Bias

Compact Current Modeling of Fully Depleted Symmetric Double-Gate Metal–Oxide–Semiconductor Field Effect Transistors with Doped Short-Channel

Design of NAND Flash Memory Device by the Fringing Field from a Control Gate

Design Consideration of Bulk FinFETs Devices With n+/p+/n+ Gate and p+/n+ Gate for Sub-50-nm DRAM Cell Transistors

Threshold-Voltage Modeling of Double-Gate MOSFETs by Considering Drain Bias

Impact Ionization Behavior in Bulk Fin Field Effect Transistors with Fin Body Width and Bias Conditions

Programming/Erasing Characteristics of 45 nm NOR-Type Flash Memory Based on SOI FinFET Structure

Device Design Consideration for 50 nm Dynamic Random Access Memory Using Bulk FinFET

Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

A Study on the Utilization of Color Theories in Kurt Schwitters’ Collages

A Study on the Structural Transformation of Composition and Its Aesthetics in Roy Lichtenstein’s Early Pop Comic Strips(1961-65)

Deleuze’s Anti-Platonist Concepts : Its Possibility as Tool for the Interpretation of Modern Art

A Study on Men’s Hair Styles and Their Plastic Beauty in Goguryeo Tomb Murals - Focused on the Relations with China and Changing Process

Threshold-Voltage Modeling of Bulk FinFETs by Considering Charge-Sharing and Surface Potential

Interpretation of Picasso's Collages by R. E. Krauss and T. J. Clark's Views of Radical Art History

Threshold Voltage Modeling of Double-Gate MOSFETs by Considering Barrier Lowering

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