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Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface

Journal of electronic materials, 1995-04, Vol.24 (4), p.303-309

1995

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Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

IEEE electron device letters, 1997-05, Vol.18 (5), p.206-208

1997

Volltextzugriff (PDF)

Models for electron and hole mobilities in MOS accumulation layers

IEEE transactions on electron devices, 1999-08, Vol.46 (8), p.1749-1759

1999

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A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

IEEE electron device letters, 2003-04, Vol.24 (4), p.257-259

2003

Volltextzugriff (PDF)

Computationally efficient models for quantization effects in MOS electron and hole accumulation layers

IEEE transactions on electron devices, 1998-07, Vol.45 (7), p.1487-1493

1998

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An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers

IEEE transactions on electron devices, 1998-02, Vol.45 (2), p.502-511

1998

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A physically-based model for quantization effects in hole inversion layers

IEEE transactions on electron devices, 1998-01, Vol.45 (1), p.179-186

1998

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An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si

IEEE transactions on electron devices, 2000-03, Vol.47 (3), p.643-645

2000

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Temperature dependence characterization of effective electron and hole mobilities in the accumulation layers of n- and p-type MOSFET's

IEEE transactions on electron devices, 1999-06, Vol.46 (6), p.1290-1294

1999

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A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS devices

IEEE transactions on electron devices, 1997-07, Vol.44 (7), p.1172-1173

1997

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Experimental determination of electron and hole mobilities in MOS accumulation layers

IEEE electron device letters, 1997-05, Vol.18 (5), p.200-202

1997

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First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories

2012 IEEE International Conference on IC Design & Technology, 2012, p.1-3

2012

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Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

2008 Symposium on VLSI Technology, 2008, p.136-137

2008

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Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications

2011 3rd IEEE International Memory Workshop (IMW), 2011, p.1-4

2011

Volltextzugriff (PDF)

An embedded 90nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

2002

Volltextzugriff (PDF)

An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

Digest. International Electron Devices Meeting, 2002, p.927-930

2002

Volltextzugriff (PDF)

Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers

1997 IEEE International Conference on Microelectronic Test Structures Proceedings, 1997, p.165-168

1997

Volltextzugriff (PDF)

High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability

2012 4th IEEE International Memory Workshop, 2012, p.1-4

2012

Volltextzugriff (PDF)

Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface : III-IV nitrides and silicon carbide

Journal of electronic materials, 1995, Vol.24 (4), p.303-309

1995

Volltextzugriff (PDF)

Reliability Study of Split Gate Silicon Nanocrystal Flash EEPROM

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007, p.75-76

2007

Volltextzugriff (PDF)

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

2008 Joint Non-Volatile Semiconductor Memory Workshop and International Conference on Memory Technology and Design, 2008, p.59-60

2008

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16Mb Split Gate Flash Memory with Improved Process Window

2009 IEEE International Memory Workshop, 2009, p.1-2

2009

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Optimization of 90nm Split Gate Nanocrystal Non-Volatile Memory

2007 22nd IEEE Non-Volatile Semiconductor Memory Workshop, 2007, p.77-78

2007

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Temperature characterization and modeling of electron and hole mobilities in MOS accumulation layers

56th Annual Device Research Conference Digest (Cat. No.98TH8373), 1998, p.20-21

1998

Volltextzugriff (PDF)

Depleting plasmacytoid dendritic cells reduces local type I interferon responses and disease activity in patients with cutaneous lupus

Science translational medicine, 2021-05, Vol.13 (595)

2021

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Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface

Experimental determination of threshold voltage shifts due to quantum mechanical effects in MOS electron and hole inversion layers

Models for electron and hole mobilities in MOS accumulation layers

A new combination-erase technique for erasing nitride based (SONOS) nonvolatile memories

Computationally efficient models for quantization effects in MOS electron and hole accumulation layers

An improved technique and experimental results for the extraction of electron and hole mobilities in MOS accumulation layers

A physically-based model for quantization effects in hole inversion layers

An experimental study of the effect of quantization on the effective electrical oxide thickness in MOS electron and hole accumulation layers in heavily doped Si

Temperature dependence characterization of effective electron and hole mobilities in the accumulation layers of n- and p-type MOSFET's

A simple model for quantum mechanical effects in hole inversion layers in silicon PMOS devices

Experimental determination of electron and hole mobilities in MOS accumulation layers

First-ever high-performance, low-power 32-bit microcontrollers with embedded nanocrystal flash and enhanced EEPROM memories

Embedded split-gate flash memory with silicon nanocrystals for 90nm and beyond

Highly Optimized Nanocrystal-Based Split Gate Flash for High Performance and Low Power Microcontroller Applications

An embedded 90nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

An embedded 90 nm SONOS nonvolatile memory utilizing hot electron programming and uniform tunnel erase

Test structure and methodology for experimental extraction of threshold voltage shifts due to quantum mechanical effects in MOS inversion layers

High Performance Nanocrystal Based Embedded Flash Microcontrollers with Exceptional Endurance and Nanocrystal Scaling Capability

Characterization and optimization of the SiO2/SiC metal-oxide semiconductor interface : III-IV nitrides and silicon carbide

Reliability Study of Split Gate Silicon Nanocrystal Flash EEPROM

Si Nanocrystal Split Gate Technology Optimization for High Performance and Reliable Embedded Microcontroller Applications

16Mb Split Gate Flash Memory with Improved Process Window

Optimization of 90nm Split Gate Nanocrystal Non-Volatile Memory

Temperature characterization and modeling of electron and hole mobilities in MOS accumulation layers

Depleting plasmacytoid dendritic cells reduces local type I interferon responses and disease activity in patients with cutaneous lupus

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